H. van Meer

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications

Fully-Depleted (FD) Silicon-on-Insulator (SOI) has become very attractive for deep submicron CMOS applications because of its quasi-ideal properties. Scaling FD SOI involves, amongst many other technology parameters, reducing the thickness of the silicon film. However, thinning the SOI film down to 50 nm or below may result in high series resistance or even full consumption of the silicon during the salicidation process. Therefore, a dedicated device architecture is needed like for example the raised gate/source/drain (G/S/D) device architecture. The authors have fabricated FD SOI transistors on top of an ultra-thin silicon film of 30 nm with gate lengths down to 0.1 /spl mu/m. After a short description of the device fabrication, the electrical results on DC and HF performance are presented and discussed.Fully-Depleted (FD) Silicon-on-Insulator (SOI) has become very attractive for deep submicron CMOS applications because of its quasi-ideal properties. Scaling FD SOI involves, amongst many other technology parameters, reducing the thickness of the silicon film. However, thinning the SOI film down to 50 nm or below may result in high series resistance or even full consumption of the silicon during the salicidation process. Therefore, a dedicated device architecture is needed like for example the raised gate/source/drain (G/S/D) device architecture. The authors have fabricated FD SOI transistors on top of an ultra-thin silicon film of 30 nm with gate lengths down to 0.1 /spl mu/m. After a short description of the device fabrication, the electrical results on DC and HF performance are presented and discussed.

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel transistor to be equal. Scaling down the MOS transistor urges the need of including halo (or pocket) implants in the fabrication process. Due to this implant, however, the short channel MOSFET features a degraded effective mobility compared to the long channel reference device. This affects the channel-length extraction and results in unrealistic high values for the extracted effective channel-length for deep submicron transistors with high-dose halo (or pocket) implants.

Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal–oxide–semiconductor field-effect transistors

A noise overshoot phenomenon occurring in the ohmic regime is described in fully depleted and partially depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistors with 2.5 nm nitrided gate oxide. It is characterized by a peak in the current noise spectral density S1 versus the front gate voltage VGS, whereby the peak amplitude can be several orders of magnitude higher than the background 1/f noise. In addition, it is shown that the corresponding spectrum has a Lorentzian shape. Associated with this noise peak is a second maximum in the device transconductance. It is believed that the mechanism of this excess noise is similar as for the kink-related noise overshoot, found in saturation. However, the origin of this floating-body effect is believed to be related to electron valence-band tunneling through the thin dielectric and occurring for a sufficiently large gate voltage.

70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme

High-performance fully-depleted SOI CMOS transistors have been realized on a 28 nm ultra thin silicon substrate with a physical gate length of 70 nm and a post NO-annealed gate oxide of 1.4 nm. A new fabrication scheme, the spacer/replacer scheme, has been used to optimize the device performance of the ultra thin-film SOI transistors. Excellent device performance has been obtained: I/sub on/ equals 711 /spl mu/A//spl mu/m and 350 /spl mu/A//spl mu/m at I/sub off/=16 nA//spl mu/m for nMOS and pMOS, respectively. The unloaded ring oscillator gate-delay is 14.5 ps at V/sub DD/=1.2 V.

The 1/f/sup 1.7/ noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide

The low-frequency noise of partially depleted silicon-on-insulator (SOI) MOSFETs is studied in the ohmic regime. In the frequency range 0.7 Hz /spl les/ f /spl les/ 50 Hz, a power spectral density is observed which follows a 1/f/sup n/ law, with n /spl sim/ 1.7 for a broad range of operation conditions. This noise is to be distinguished from the usual 1/f-like noise, occurring at higher frequency for devices with a length smaller than 1 /spl mu/m. From the dependence on the gate voltage and device length, it is concluded that the 1/f/sup 1.7/ noise is of the McWhorter type and, therefore, is generated by carrier exchange between the front channel and traps in the 2.5 nm NO gate oxide. This type of noise is absent in the back-channel or in the gate current. A model will be presented, from which it is derived that the responsible traps are most likely associated with the polysilicon gate/oxide interface and, furthermore, show a steep concentration profile over a small depth range. A similar noise behavior is observed in bulk devices with thin gate dielectrics.

The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

In this work, we introduce the Spacer/Replacer concept, a new concept to improve the device performance of ultrathin-film fully-depleted (FD) SOI CMOS transistors. High-performance FD SOI CMOS transistors are demonstrated with a silicon film thickness of 30 nm and physical gate-lengths down to 0.1 /spl mu/m. The approach uses selective epitaxial growth of silicon to form raised source/drains while avoiding the simultaneous formation of a T-shaped poly-Si gate. In addition, the introduced concept eases the integration issues related to the ultrathin silicon film.

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and supply voltage of 1.5 V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) extension dose, S/D HDD dose and spike RTA on the reduction of series resistance and poly-depletion effect is studied. The role of the HALO implantation in optimization is investigated in detail.

Strain mapping of Si devices with stress memorization processing

Dual lens dark field electron holography and Moire fringe mapping from dark field scanning transmission electron microscopy are used to map strain distributions at high spatial resolution in Si devices processed with stress memorization techniques (SMT). It provides experimental evidence that strain in the Si channel is generated by dislocations resulting from SMT. The highest value of strain, up to 1.1% (1.9 GPa in stress) occurs at the Si surface along the channel direction: ⟨110⟩. An increase of ∼0.2% strain in the channel is observed after removing the poly-Si gate through the replacement high-k metal gate process.

A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with Halos or pockets

The exact solution of the two-dimensional (2-D) Poissons equation has been analytically derived for fully-depleted (FD) SOI MOSFETs with Halos or pockets. The approach uses a three-zone Greens function solution technique. Explicit equations for the 2-D electrical potential as well as for both front- and back-side threshold voltages have been derived. The accuracy of the equations has been verified by a 2-D numerical device simulator. From the presented results, it can be concluded that the analytically derived model for the electric potential and threshold voltages are in good agreement with 2-D numerical simulation data.