Guy M. Cohen

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures

In this paper, we describe several critical aspects of wafer scale or die level bonding to demonstrate: (1) low temperature bonding for planar layer interconnections; (2) low temperature bonding for non-planar layer sealing; (3) alignment and transfer of process sub-assemblies such as BEOL wiring, MEMS cavity or active device structures; and (4) integration methodology for fabrication of these layer stacks into 3D circuits and MEMS. We also show examples of how layer stacking protocols using wafer bonding technology provides a capability to integrate mixed materials and technologies potentially adaptable to many other applications. In addition, we demonstrate that in order to evaluate the influence of bonding on the electrical integrity of the transferred ICs, state-of-the art circuits, such as short channel length MOSFETs or ring oscillators, should be tested as they are most sensitive to environmental/processing changes.

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.

Nanowire metal-oxide-semiconductor field effect transistor with doped epitaxial contacts for source and drain

The authors report the fabrication of a p-field effect transistor (FET) and an n-FET with a silicon nanowire channel and doped silicon source and drain regions. The silicon nanowires were synthesized by the vapor-liquid-solid method. For p-FETs the source and drain regions were formed by adding boron doped silicon to the unintentionally doped nanowire body at predefined locations using in situ doped silicon epitaxy. For n-FETs the epitaxial source and drain regions were grown undoped and were later implanted with P and As. The measured Id-Vg characteristics of the devices exhibited unipolar transport, while reference FETs made with nanowires from the same batch but with Schottky (metal) contacts exhibited ambipolar characteristics.

4-bit per cell NROM reliability

The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme

Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

Elastic strain relaxation in free-standing SiGe/Si structures

We have investigated elastic strain relaxation, i.e., strain relaxation without the introduction of dislocations or other defects, in free-standing SiGe/Si structures. We fabricated free-standing Si layers supported at a single point by an SiO2 pedestal and subsequently grew an epitaxial SiGe layer. The measured strain relaxation of the SiGe layer agrees well with that calculated using a force-balance model for strain sharing between the SiGe and strained Si layers. We report strained Si layers with biaxial tensile strain equal to 0.007 and 0.012.

Characterization of the silicon on insulator film in bonded wafers by high resolution x-ray diffraction

High resolution x-ray diffraction (HRXRD) is proposed as a nondestructive tool for the characterization of the silicon on insulator (SOI) film in bonded wafers. Although the bonded stack may consist of many amorphous layers, the measured diffraction spectra only show the crystalline SOI layer, thus providing a direct measurement of the film. We have demonstrated that HRXRD is capable of accurately measuring the film thickness, the tilt of the film planes with respect to the substrate planes, and the rotation misalignment of the bonded film with respect to the carrier substrate. SOI films with thicknesses down to 30 nm were readily measured with accuracy better than 1%. It is shown that an angular separation between the layer and the substrate diffraction peaks is maintained due to an unintentional miscut which usually exists in the starting wafers used for bonding. This angular separation is unique to bonded wafers as opposed to separation by implanted oxygen (SIMOX) wafers where the layer and substrate p...

High-resolution x-ray diffraction for characterization and monitoring of silicon-on-insulator fabrication processes

High-resolution x-ray diffraction (HRXRD) was used to monitor silicon-on-insulator (SOI) device fabrication processes. The use of HRXRD is attractive since it is nondestructive and can be applied directly to product wafers. We show the usefulness of this technique for the characterization of amorphizing implants for shallow junctions, solid phase recrystallization of implanted junctions, cobalt-silicide formation, and oxidation; all are critical processes for complementary metal oxide semiconductor device fabrication on SOI. We also found the technique applicable to multilayered SOI structures fabricated by wafer bonding, where the tilt and rotation of each SOI layer with respect to the handle substrate, allowed us to obtain independent measurements of each SOI film.