Elio Consoli

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies

In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.

General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit

In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of leakage and layout parasitics on the optimization of the circuits. The tradeoffs between leakage, area, clock load, delay, and other interesting properties are extensively discussed. The investigation permits to derive several considerations on each FF class and to identify the best topologies for a targeted application.

Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷40 % energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations.

An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits

In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.

From energy-delay metrics to constraints on the design of digital circuits

In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energy-efficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of EiDj metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing EiDj metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results. Copyright

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.

Metrics and design considerations on the energy-delay tradeoff of digital circuits

In this paper, general metrics of the energy-delay (E-D) tradeoff in digital VLSI circuits are discussed. More specifically, the general class of metrics EiDj with arbitrary exponents is adopted and evaluated for various commercial microprocessors. Results indicate that practical circuits are designed by minimizing a wider range of metrics compared to the ED or ED2 metrics usually assumed in the literature. Hence, the general metrics EiDj describes the energy-delay tradeoff in a more realistic way. An interesting interpretation of the adopted metrics is provided to gain an insight into the relationship between energy and delay in energy-efficient designs. Various properties are also derived analytically by resorting to the Logical Effort method. Simulations on a 65-nm technology are performed to exemplify and validate the theoretical results.

DET FF topologies: A detailed investigation in the energy-delay-area domain

In this paper, a comparison of representative Dual-Edge-Triggered flip-flop topologies is carried out in a 65-nm CMOS technology. The energy efficiency is analyzed together with other aspects, such as the area-delay tradeoff, leakage and clock-load, which are typically neglected in previous works. The investigation highlights the impact of effects that become dominant in nanometer technologies (e.g., local interconnects, leakage) and allows for identifying the most effective FFs belonging to the DET class, as well as to evaluate the suitability of DET topologies for real applications.

Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency

In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.