Melita Pennisi

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay dependence on fan-in, fan-out, and sizing in sub-100-nm technologies. Simple but reasonably accurate models are derived to capture the basic dependences. The effect of process variations in transistor stacks is analytically modeled and analyzed in detail. The impact of both interdie and intradie variations is evaluated and discussed. Interestingly, the input capacitance of static and dynamic logic is shown to be rather insensitive to variations. The delay variability was also shown to be a weak function of the input rise/fall time and load. Analysis shows that domino logic circuits suffer from a doubled variability as compared to the static CMOS logic style. The positive feedback associated with the keeper transistor is shown to be responsible for the variability increase, which, in turn, limits the speed performance. This adds to the well-known speed degradation due to the current contention associated with the keeper transistor. Monte Carlo simulations on a 90-nm technology, including layout parasitics, are performed to validate the results.

A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates

In this paper, a simple approach to reduce delay variations in domino logic gates is proposed. Previous analysis by the same authors showed that delay variations in domino logic are mainly due to the feedback loop implemented by the keeper transistor and the output inverter gate. Accordingly, the proposed strategy aims at reducing the loop gain associated with this feedback loop, and hence its impact on delay variations. In particular, a simple modified keeper is proposed to reduce the loop gain while keeping the same silicon area, noise margin, and nominal performance. The resulting delay variations associated with keeper insertion are shown to be lowered by approximately 50%. The proposed approach is assessed by means of simulations in 65-nm and 90-nm commercial CMOS technologies.

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor alpha les 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of alpha on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of alpha (alpha = 0, 0.5, and 1) in a 0.5 mum CMOS technology with plusmn1.65-V supply voltage. Experimental results show (for alpha = 1 ) a THD of - 57 dB (HD2=-70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 muA/V and a power consumption of 3.2 mW.

Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier

The paper presents the derivation of Miller formulas for weakly nonlinear feedback networks. The expressions found are simple and compact and constitute a generalization of the well- known linear case. As an application example, the formulas are applied to a common-emitter amplifier to straightforwardly derive the closed-form expressions of second- and third-harmonic distortion factors. The results found, validated by Spectre simulations with a VBIC bipolar model, allow to understand in depth the contribution of each nonlinear element.

Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion

Theoretical study and design strategy for Wien oscillator circuits are presented. The analysis takes into account nonlinearities and allows to define an optimum design procedure minimizing distortion. The accuracy and viability of both the proposed analysis and design approach are confirmed experimentally.

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.

AMOLED pixel driver circuits based on poly-Si TFTs: A comparison

In this paper, four different driver circuits for an active matrix organic light-emitting diode (AMOLED) pixel based on thin film transistor (TFT) technology are analyzed and compared. In particular, the comparison analyzed accuracy, driving speed, power consumption and area occupied. Moreover, in order to allow array simulations, the RC equivalent models of the pixel were also derived. The results were achieved considering a QVGA display (320x240), a line frequency of 60Hz, and were verified by simulations with AIM-SPICE.

Design guidelines for high-speed Transmission-gate latches: Analysis and comparison

In this paper we present a pencil-and-paper procedure to design transmission-gate latches for high-speed performance. The procedure, based on the Logical Effort approach, independently optimizes the master and slave section to get minimum delay, sizing all transistors in the critical path. The other devices, like keeper transistors or switches in the positive feedback networks, are sized with minimum width thus providing only a negligible capacitive load to the internal nodes. Simulations are performed on a PowerPC 603 master-slave latch designed with a 90-nm technology provided by STMicroelectronics, and the overall good performance of the proposed procedure compared to other design strategies is verified.

Distortion analysis in the frequency domain of a G m -C biquad

Evaluation of the harmonic distortion in the frequency domain for a G m-C biquad filter is carried out by using a phasor notation. This approach allows a pencil and paper analysis, thus yielding a clever understanding of harmonic generation and highlighting the role of each single contribution. Theoretical results are compared and validated through spectre simulations.

Analysis and evaluation of harmonic distortion in the tunnel diode oscillator

A simple technique to evaluate the linearity performance of a tunnel diode oscillator is presented. The approach is based on the phasor method and avoids redundant computations and/or iterations required by traditionally adopted mathematical tools. Equations found are simply derived, extend our knowledge on harmonics generation and are particularly useful for the designer. A design example is provided and simulations are found in good agreement with expected results