Gianluca Giustolisi

A detailed analysis of power-supply noise attenuation in bandgap voltage references

This paper discusses the power-supply noise attenuation (PSNA) in the frequency domain of four kinds of bandgap voltage reference that represent the basis of typical voltage references. This performance parameter becomes a fundamental design criterion in high-frequency applications where, due to the reduction in the loop gain, spurious signals coming from the power supply cannot be adequately rejected. Precise and simple models, useful for pencil and paper analysis are hereby developed for the four analyzed topologies and, where possible, compensation techniques are discussed. Moreover, the four topologies are compared in detail highlighting both their main features and drawbacks.

Behavioral modeling of statistical phenomena of single-photon avalanche diodes

In this paper, we present an accurate behavioral model for simulating single-photon avalanche diodes (SPADs). The device operation is described using the Verilog-A description language, which is an analog extension of the common digital hardware description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of an SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach showing a good matching between the behavior of the proposed model and experimental results reported in the literature. Copyright

An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits

In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.

Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators

This paper presents a general methodology for compensating LDO regulators which exploits a current amplifier to effectively multiply the Miller capacitor. After a general theoretical analysis that takes into account both the external and internal loop stability, it is examined the feasibility of applying this kind of compensation in different LDO applications, showing the role of the design parameters and proposing a specific design procedure for each practical cases which differ in terms of load capacitance and the adoption of a decoupling voltage buffer. Simulations and experimental results which validate the methodology are also included.

Design and comparison of very low-voltage CMOS output stages

This paper analyzes and compares CMOS output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations.

Resolution of a current-mode algorithmic analog-to-digital converter

Errors limiting the resolution of current-mode algorithmic analog-to-digital converters are mainly related to current mirror operation. While systematic errors can be minimized by proper circuit techniques, random sources are unavoidable. In this paper a statistical analysis of the resolution of a typical converter is carried out taking into account process tolerances. To support the analysis, a 4-bit ADC, realized in a 0.35-/spl mu/m CMOS technology, was exhaustively simulated. Results were found to be in excellent agreement with theoretical derivations.

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.

Analysis and optimization of gain-boosted telescopic amplifiers

A thorough analysis of the behavior of a simple gain-boosted telescopic amplifier in terms of both the frequency and time domain is performed. The well-known slow-settling component is analyzed and a constraint for eliminating its effect is also given. Moreover, a procedure for designing the amplifier, based on the comparison of its time response to the time response of a two-pole system is reported, too.

CMRR frequency response of CMOS operational transconductance amplifiers

In this paper an accurate and complete analysis of the CMRR for the most commonly used CMOS OTAs has been carried out. The analysis provides equations which can profitably be used in the design of high-accuracy integrated amplifiers to be employed in instrumentation circuits. The analysis shows that the CMRR of these circuits is highly affected by two poles which are caused by the zeros of the common-mode gain. By using the Spice simulator and the models of a 1.2-/spl mu/m CMOS process, we have found that the calculated frequency response of CMRR well fits the simulated curves for input frequencies as high as 100 MHz.

Detailed frequency analysis of power supply rejection in Brokaw bandgap

A detailed frequency analysis of Power Supply Rejection (PSR) in Brokaw bandgap voltage reference is carried out. The knowledge of the frequency behavior in a voltage reference becomes mandatory to the designer especially in RF or digital environment where disturbs coming from supply lines becomes more evident. Precise and simple models, useful for pencil and paper analysis, are developed and a compensation technique for improving the circuit frequency performance is also discussed. Results are validated by comparing the implemented models with the actual circuit by means of the SPECTRE simulator.