Elyakim Kassel

Optimized overlay metrology marks: theory and experiment

In this paper, we provide a detailed analysis of overlay metrology mark and find the mapping between various properties of mark patterns and the expected dynamic precision and fidelity of measurements. We formulate the optimality criteria and suggest an optimal overlay mark design in the sense of minimizing the Cramer-Rao lower bound on the estimation error. Based on the developed theoretical results, a new overlay mark family is proposed-the grating marks. A thorough testing performed on the new grating marks shows a strong correlation with the underlying theory and demonstrate the superior quality of the new design over the overlay patterns used today.

Performance study of new segmented overlay marks for advanced wafer processing

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

In-chip overlay metrology in 90 nm production

We have inserted, measured and demonstrated good metrology performance on in-die overlay targets on product wafers. It is shown that scanner aberration induced pattern placement errors (PPE) can be measured, simulated and validated by CD-SEM, but the magnitude of the effect on late generation scanners is small - of the order of /spl sim/1.5 nm peak to peak across the slit. It is observed that in-die overlay data contains additional sources of variation beyond PPE and the results have been verified by SEM. It is demonstrated that current practices based on linear models do not capture in-die variations which significantly impacts model residuals. Currently, in-die target insertion is an insurance policy which enables in-die trouble shooting when process issues are suspected and will potentially improve lot dispositioning in the future.

MAGIC: a European program to push the insertion of maskless lithography

With the willingness of the semiconductor industry to push manufacturing costs down, the mask less lithography solution represents a promising option to deal with the cost and complexity concerns about the optical lithography solution. Though a real interest, the development of multi beam tools still remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the mask less technology. The aim of the program is to develop multi beam systems from MAPPER and IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper draws the present status of multi beam lithography and details the content and the objectives of the MAGIC project.

AIM technology for Non-Volatile Memories microelectronics devices

Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.

Novel at-design-rule via-to-metal overlay metrology for 193-nm lithography

The effect of scanner aberrations on pattern placement errors (PPE) in the copper interconnect lithography process is studied both in simulations and experimentally. A new grating-based overlay mark, advanced imaging metrology, enables measuring device feature overlay. It is shown that the grating mark exhibits superior performance over conventional box-in-box marks. A comparison between grating-based optical and direct CD scanning electron microscopic (SEM) device overlay measurements was done. Both CD SEM and grating mark optical measurements show sensitivity to PPE. Good matching between the new grating target and device overlays was demonstrated.

In-field overlay uncertainty contributors: a back end study

In this publication, the contributors to in-field overlay metrology uncertainty have been parsed and quantified on a back end process and compared with results from a previous front end study1. Particular focus is placed on the unmodeled systematics, i.e. the components which contribute to residuals in a linear model after removal of random errors. These are the contributors which are often the most challenging to quantify and are suspected to be significant in the model residuals. The results show that in both back and front end processes, the unmodeled systematics are the dominant residual contributor, accounting for 60 to 70% of the variance, even when subsequent exposures are on the same scanner. A higher order overlay model analysis demonstrates that this element of the residuals can be further dissected into correctible and non-correctible high order systematics. A preliminary sampling analysis demonstrates a major opportunity to improve the accuracy of lot dispositioning parameters by transitioning to denser sample plans compared with standard practices. Field stability is defined as a metric to quantify the field to field variability of the intrafield correctibles.

A comparison of methods for in-chip overlay control at the 65-nm node

Overlay metrology for production line-monitor and advanced process control (APC) has been dominated by 4-corner box-in-box (BiB) methods for many years. As we proceed following the ITRS roadmap with the development of 65 nm technologies and beyond, it becomes apparent that current overlay methodologies are becoming inadequate for the stringent requirements that lie ahead. It is already apparent that kerf metrology of large scale BiB structures does not correlate well with in-chip design-rule features. The recent introduction of the Advanced Imaging Metrology (AIM) target, utilizing increased information content and advanced design and process compatibility, has demonstrated significant improvements in precision and overlay mark fidelity (OMF) in advanced processes. This paper compares methodologies and strategies for addressing cross-field variation of overlay and pattern placement issues. We compare the trade-offs of run-time intra-field sampling plans and the use of off-line lithography characterization and advanced modeling analysis, and propose new methodologies to address advanced overlay metrology and control.

Improved overlay metrology device correlation on 90-nm logic processes

Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

Overlay accuracy: a metal layer study

While overlay precision has received much focus in the past, overlay accuracy has become more significant with shrinking process budgets. One component of accuracy is the difference between pre-etch (DI) and post-etch (FI) overlay, which is a function of wafer processing parameters. We investigated a specific case of overlay between metal and contact layers of a 0.16 mm SRAM process. This layer was chosen because a significant amount of wafer contraction was observed between DI and FI, resulting in as much as 30nm of DI-FI overlay difference. The purpose of the study was to characterize the systematic DI-FI differences and gain understanding of the wafer processing parameters that affect the DI-FI differences. A designed experiment showed how certain overlay mark widths were less sensitive to processing parameters. AFM profiles of the prior-level overlay marks identified issues with mark widths 1.0um or smaller. By performing localized etches on the inner vs. outer marks of the overlay targets, it was noted that the majority of the wafer contraction was induced by etching the outer (prior level) mark. Production measurements at photo and etch showed the wafer contraction to be fairly stable over a month timeframe and independent of device and exposure tool, though large fluctuation shifts in wafer contraction were noted over a nine-month period. The methods used in this study can be helpful in understanding other DI-FI processing issues.