Mike Adel

Optimized overlay metrology marks: theory and experiment

In this paper, we provide a detailed analysis of overlay metrology mark and find the mapping between various properties of mark patterns and the expected dynamic precision and fidelity of measurements. We formulate the optimality criteria and suggest an optimal overlay mark design in the sense of minimizing the Cramer-Rao lower bound on the estimation error. Based on the developed theoretical results, a new overlay mark family is proposed-the grating marks. A thorough testing performed on the new grating marks shows a strong correlation with the underlying theory and demonstrate the superior quality of the new design over the overlay patterns used today.

Improved overlay control through automated high-order compensation

As Moores Law drives CD smaller and smaller, overlay budget is shrinking rapidly. Furthermore, the cost of advanced lithography tools prohibits usage of latest and greatest scanners on non-critical layers, resulting in different layers being exposed with different tools; a practice commonly known as mix and match. Since each tool has its unique signature, mix and match becomes the source of high order overlay errors. Scanner alignment performance can be degraded by a factor of 2 in mix and match, compared to single tool overlay operation. In a production environment where scanners from different vendors are mixed, errors will be even more significant. Mix and match may also be applied to a single scanner when multiple illumination modes are used to expose critical levels. This is because different illuminations will have different impact to scanner aberration fingerprint. The semiconductor technology roadmap has reached a point where such errors are no longer negligible. Mix and match overlay errors consist of scanner stage grid component, scanner field distortion component, and process induced wafer distortion. Scanner components are somewhat systematic, so they can be characterized on non product wafers using a dedicated reticle. Since these components are known to drift over time it becomes necessary to monitor them periodically, per scanner, per illumination. In this paper, we outline a methodology for automating characterization of mix and match errors, and a control system for real-time correction.

Differential signal scatterometry overlay metrology: an accuracy investigation

The overlay control budget for the 32nm technology node will be 5.7nm according to the ITRS. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further technology development is required to bring it to this level. In this work we present results of a study of an alternative technology for overlay metrology - Differential signal scatterometry overlay (SCOL). Theoretical considerations show that overlay technology based on differential signal scatterometry has inherent advantages, which will allow it to achieve the 32nm technology node requirements and go beyond it. We present results of simulations of the expected accuracy associated with a variety of scatterometry overlay target designs. We also present our first experimental results of scatterometry overlay measurements, comparing this technology with the standard imaging overlay metrology technology. In particular, we present performance results (precision and tool induced shift) and address the issue of accuracy of scatterometry overlay. We show that with the appropriate target design and algorithms scatterometry overlay achieves the accuracy required for future technology nodes.

Performance study of new segmented overlay marks for advanced wafer processing

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

In-chip overlay metrology in 90 nm production

We have inserted, measured and demonstrated good metrology performance on in-die overlay targets on product wafers. It is shown that scanner aberration induced pattern placement errors (PPE) can be measured, simulated and validated by CD-SEM, but the magnitude of the effect on late generation scanners is small - of the order of /spl sim/1.5 nm peak to peak across the slit. It is observed that in-die overlay data contains additional sources of variation beyond PPE and the results have been verified by SEM. It is demonstrated that current practices based on linear models do not capture in-die variations which significantly impacts model residuals. Currently, in-die target insertion is an insurance policy which enables in-die trouble shooting when process issues are suspected and will potentially improve lot dispositioning in the future.

The challenges of transitioning from linear to high-order overlay control in advanced lithography

In the lithography section of the ITRS 2006 update, at the top of the list of difficult challenges appears the text overlay of multiple exposures including mask image placement. This is a reflection of the fact that today overlay is becoming a major yield risk factor in semiconductor manufacturing. Historically, lithographers have achieved sufficient alignment accuracy and hence layer to layer overlay control by relying on models which define overlay as a linear function of the field and wafer coordinates. These linear terms were easily translated to correctibles in the available exposure tool degrees of freedom on the wafer and reticle stages. However, as the 45 nm half pitch node reaches production, exposure tool vendors have begun to make available, and lithographers have begun to utilize so called high order wafer and field control, in which either look up table or high order polynomial models are modified on a product by product basis. In this paper, the major challenges of this transition will be described. It will include characterization of the sources of variation which need to be controlled by these new models and the overlay and alignment sampling optimization problem which needs to be addressed, while maintaining the ever tightening demands on productivity and cost of ownership.

Overlay metrology for double patterning processes

The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOLTM [1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT very challenging. In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique (SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in double patterning processes.

Novel at-design-rule via-to-metal overlay metrology for 193-nm lithography

The effect of scanner aberrations on pattern placement errors (PPE) in the copper interconnect lithography process is studied both in simulations and experimentally. A new grating-based overlay mark, advanced imaging metrology, enables measuring device feature overlay. It is shown that the grating mark exhibits superior performance over conventional box-in-box marks. A comparison between grating-based optical and direct CD scanning electron microscopic (SEM) device overlay measurements was done. Both CD SEM and grating mark optical measurements show sensitivity to PPE. Good matching between the new grating target and device overlays was demonstrated.

Diffraction order control in overlay metrology : a review of the roadmap options

Resolution enhancement in advanced optical lithography will reach a new plateau of complexity at the 32 nm design rule manufacturing node. In order to circumvent the fundamental optical resolution limitations, ultra low k1 printing processes are being adopted, which typically involve multiple exposure steps. Since alignment performance is not fundamentally limited by resolution, it is expected to yield a greater contribution to the effort to tighten lithographic error budgets. In the worst case, the positioning budget usually allocated to a single patterning step is divided between two. A concurrent emerging reality is that of high order overlay modeling and control. In tandem with multiple exposures, this trend creates great pressure to reduce scribeline target real estate per exposure. As the industry migrates away from metrology targets formed from large isolated features, the adoption of dense periodic array proxies brings improved process compatibility and information density as epitomized by the AIM target1. These periodic structures enable a whole range of new metrology sensor architectures, both imaging and scatterometry based, that rely on the principle of diffraction order control and which are no longer aberration limited. Advanced imaging techniques remain compatible with side-by-side targets while scatterometry methods require grating-over-grating targets. In this paper, a number of different imaging and scatterometry architectures are presented and compared in terms of random errors, systematic errors and scribespace requirements. It is asserted that an optimal solution must combine the TMU peak performance capabilities of scatterometry with the cost of ownership advantages of target size and multi-layer capabilities of imaging.

In field overlay uncertainty contributors

In this publication, the contributors to in-field overlay metrology uncertainty have been parsed and quantified in a specific case study. Particular focus is placed on the unmodeled systematics, i.e. the components which contribute to residuals in a linear model after removal of random errors. These are the contributors which are often the most challenging to quantify and are suspected to be significant in the model residuals. The results show that even in a relatively clean front end process, the unmodeled systematics are the dominant residual contributor, accounting for 60 to 70% of the variance. Given the above results, new sampling and modeling methods are proposed which have the potential to improve the accuracy of modeled correctibles and lot dispositioning parameters.