Mark Ghinovker

Optimized overlay metrology marks: theory and experiment

In this paper, we provide a detailed analysis of overlay metrology mark and find the mapping between various properties of mark patterns and the expected dynamic precision and fidelity of measurements. We formulate the optimality criteria and suggest an optimal overlay mark design in the sense of minimizing the Cramer-Rao lower bound on the estimation error. Based on the developed theoretical results, a new overlay mark family is proposed-the grating marks. A thorough testing performed on the new grating marks shows a strong correlation with the underlying theory and demonstrate the superior quality of the new design over the overlay patterns used today.

Performance study of new segmented overlay marks for advanced wafer processing

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

Novel at-design-rule via-to-metal overlay metrology for 193-nm lithography

The effect of scanner aberrations on pattern placement errors (PPE) in the copper interconnect lithography process is studied both in simulations and experimentally. A new grating-based overlay mark, advanced imaging metrology, enables measuring device feature overlay. It is shown that the grating mark exhibits superior performance over conventional box-in-box marks. A comparison between grating-based optical and direct CD scanning electron microscopic (SEM) device overlay measurements was done. Both CD SEM and grating mark optical measurements show sensitivity to PPE. Good matching between the new grating target and device overlays was demonstrated.

Overlay mark optimization using the KTD signal simulation system.

As the overlay performance and accuracy requirements become tighter, the impact of process parameters on the target signal becomes more significant. Traditionally, in order to choose the optimum overlay target, several candidates are placed in the kerf area. The candidate targets are tested under different process conditions, before the target to be used in mass production is selected. The varieties of targets are left on the mass production mask and although they will not be used for overlay measurements they still consume kerf real estate. To improve the efficiency of the process we are proposing the KTD (KLA-Tencor Target Designer). It is an easy to use system that enables the user to select the optimum target based on advanced signal simulation. Implementing the KTD in production is expected to save 30% of kerf real estate due to more efficient target design process as well as reduced engineering time. In this work we demonstrate the capability of the KTD to simulate the Archer signal in the context of advanced DRAM processes. For several stacks we are comparing simulated target signals with the Archer100 signals. We demonstrate the robustness feature in the KTD application that enables the user to test the target sensitivity to process changes. The results indicate the benefit of using KTD in the target optimization process.

Improved overlay metrology device correlation on 90-nm logic processes

Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

Metrology target design simulations for accurate and robust scatterometry overlay measurements

Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.

Overlay metrology performance prediction fidelity: the factors enabling a successful target design cycle

Overlay metrology performances highly depend on the detailed design of the measured target. Hence performing simulations is an essential tool for optimizing target design. We demonstrate for scatterometry overlay (SCOL) three key factors which enable consistency in ranking between simulated and measured metrology performance for target design. The first factor, to enable high fidelity simulations for the purpose of target design, is stack and topography verification of model inputs. We report in detail the best known film metrology methods required to achieve model integrity. The second factor is the method of calculation of metrology performance metrics based on target cell reflectivities from electro-magnetic (EM) simulations. These metrics enable ranking of different designs, and subsequent choice of the best performing designs among all simulated design options, the ranking methodology being the third factor. We apply the above steps to a specific stack, where five different designs have been considered. Simulated versus measured values are compared. A good agreement between simulation and measurement is achieved.

Stack and topography verification as an enabler for computational metrology target design

Computational metrology target design requires both an accurate metrology simulation engine and an accurate geometric model. This paper deals with the later. Optical critical dimension metrology and cross-section SEM are demonstrated as two useful methods of geometric model verification with differing capabilities. Specifically, a methodology is proposed which allows the metrology engineer to quantify the level of accuracy required by the model as a function of the tolerable uncertainty in the prediction of metrology performance metrics. The methodology identifies a subset of model parameters which need to be verified enabling the metrology engineer to invest the minimum effort in stack and topography verification which will lead to performing target designs on the first design round.

Test of a new sub-90-nm DR overlay mark for DRAM production

An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.