Emeka H. Amalu

Thermal interface materials for automotive electronic control unit: Trends, technology and R&D challenges

Abstract The under-hood automotive ambient is harsh and its impact on electronics used in electronic control unit (ECU) assembly is a concern. The introduction of Euro 6 standard (Latest European Union Legislation) leading to increase in power density of power electronics in ECU has even amplified the device thermal challenge. Heat generated within the unit coupled with ambient temperature makes the system reliability susceptible to thermal degradation which ultimately may result in failure. Previous investigations show that the technology of thermal interface materials (TIMs) is a key to achieving good heat conductions within a package and from a package to heat sinking device. With studies suggesting that current TIMs contribute about 60% interfacial thermal resistance, a review of engineering materials has become imperative to identify TIM that could enhance heat transfer. This paper critically reviews the state-of-the-art in TIMs which may be applicable to automotive ECU. Our review shows that carbon-nanotube (CNT) when used as the structure of TIM or TIM filler could considerably advance thermal management issues by improving heat dissipation from the ECU. This search identifies chemical vapor deposition (CVD) as a low cost process for the commercial production of CNTs. In addition, this review further highlights the capability of CVD to grow nanotubes directly on a desired substrate. Other low temperature techniques of growing CNT on sensitive substrates are also presented in this paper.

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

High temperature electronics: R&D challenges and trends in materials, packaging and interconnection technology

The development of new high temperature electronics (HTE)/systems is the key to achieving high reliability safety critical operations in aerospace, automotive and well-logging applications. Reliability issues associated with the operation of HTE devices have been shown to account for some of the recent aircraft crashes as well as failures of the electronic control Unit in modern vehicles. The reliability of electronic systems is partly dependent on its operating ambient conditions; and reliability generally decreases in harsh operating conditions. The life expectancy of components and systems is known to reduce exponentially as the operating temperature increases; adversely impacting long-term system reliability. As under-bonnet, aerospace and well-logging applications require the direct exposure of sensors to very harsh conditions - these applications demand new HTE systems which can operate reliably in harsh conditions whilst preserving their properties/functions over long operating periods. The packaging and interconnection of the new HTE systems requires better understanding of the complex interactions between HTE system parameters and specific environmental conditions. The paper presents an overview of HTE research, reviews the trends in materials, component packaging and interconnect technology. The paper also outlines the key challenges in HTE research and the outstanding R&D issues.

Prediction of damage and fatigue life of high-temperature flip chip assembly interconnections at operations

The determination of the real value of damage/plastic work density in solder joints from computer numerical modelling and its usage in fatigue life prediction models based on accumulated energy density is critical to improving the accuracy of predicted life of solder joints. Commercial ANSYS software based on three-dimensional finite element analysis (FEA) was employed to investigate damage of bonded materials of lead-free solder joints in a flip chip (FC48D6.3C457) mounted on a printed circuit board (PCB). The trend behaviour of accumulated damage and fatigue life per cycle over many accelerated thermal cycles (ATCs) are also studied. The solder bumps deformation is modelled using ANAND’s visco-plasticity and the performances of all other materials in the assembly were captured with appropriate material models. It was observed that the difference in stress magnitude and amplitude between inter-metallic compounds (IMCs) at the die side and solder bulk was highest and the presence of IMC in the joints increases bump damage which occurs in three stages during temperature cycle loading. These results demonstrate that while IMC impacts solder joint reliability, the bond at interconnect between IMC at the die side and solder bulk is most vulnerable to fatigue crack initiation and propagation. A new methodology to find accurate solder joint damage is presented. The findings show that average damage from cycle of hysteresis loop stabilisation to cycle of onset of tertiary damage demonstrates potential of being adequate in determining magnitude of the solder joint damage. However, considering that damage evolution is in three-phase, we propose the use of polynomial function to estimate plastic work damage in FC solder joints.

Investigation Of The Effects Of Reflow Profile Parameters On Lead‐free Solder Bump Volumes And Joint Integrity

The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high‐density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip‐chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad‐to‐pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead‐free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24−1 Ramp‐Soak‐Spike reflow profile, with all main effects and two‐way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer‐pitch interconnect.The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high‐density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip‐chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad‐to‐pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, an...

Numerical Investigation of Thermo-Mechanical Behaviour of Ball Grid Array Solder Joint at High Temperature Excursion

The solder joints of surface mount components (SMCs) experience thermal degradation culminating in creep and plastic shear strain deformation when subjected to cyclic temperature load over time. Degradation at the joints is due to thermal stress induced by the incompatible, differential and nonlinear expansion mismatch of the different bonded materials in the assembly. The stress magnitude influences the strain behaviour. Plastic strain response of solder joint is critical at the materials interface at the lower part of the joint due to the occurrence of wider variation in the coefficient of thermal expansion of the bonded materials and this may lead to static structural failure. The life expectancy of electronic components reduces exponentially as the operating temperature increases thus making reliability a key concern for electronic systems operating at high temperatures and in harsh environments. This paper reports on the numerical investigation of thermo-mechanical response of a critical BGA joint especially the character of plastic deformation of SnPb solder used in forming the joint as well as the joint’s high temperature reliability. The analysis uses a 3-D models to predict the effect of the transient thermal load on the static structural integrity of a single BGA joint. In this study, the base diameter of solder ball (interface between the PCB, copper pad and the solder) experienced higher damage than the top diameter interconnects. The paper provides a simplified methodology to study the reliability of BGA solder joint at high temperatures excursion.

Thermal Management Materials for Electronic Control Unit: Trends, Processing Technology and R and D Challenges

The development of advanced thermal management materials for Electronic Control Unit (ECU) is the key to achieving high reliability and thus safety critical operations in areas of ECU applications such as automotives and power systems. Thermal management issues associated with the operation of ECU at elevated temperature have accounted for some of the recent reliability concerns which have culminated in current systems failures in some automobiles. As the functions of ECU in systems have increased in recent times, the number of components per unit area on its board has also risen. High board density boosts internal heat generated per unit time in ECU ambient. The generated heat induces stress and strain at the chip interconnects due to variation in the Coefficient of Thermal Expansion (CTE) and thermal conductivity of different bonded materials in the assembly. Thermal degradation could become critical and impacts device’s efficiency. The life expectancy of electronic components reduces exponentially as the operating temperature rises thus making thermal management pivotal in electronic system reliability. Since materials’ properties vary with operating condition, material performance has become a major consideration in the design of heat dissipation mechanism in ECU. The development of advanced thermal management materials and hence improving the performance of ECU requires an in-depth understanding of the complex relationship between materials’ properties and their behaviours at elevated temperatures. The paper presents an overview of thermal management materials, review trends in material and processing technology. In addition, the paper outlines the crucial challenges in materials, cost and composite formulations and the outstanding R & D issues.

Effect of component standoff height on thermo-mechanical reliability of ball grid array (BGA) solder joints operating in high-temperature ambient

Effect of standoff height (SH) on thermo-mechanical reliability of solder joints in miniaturised surface mount components in consumer electronics which operates in high-temperature ambient is studied. This work investigates the effect of CSH on ball grid array (BGA) solder joints which operates in high homologous temperature in mission critical systems and seeks to utilise the findings of this investigation to minimise the accumulated strain energy density in the joints. The study focuses to underpin the relationship between CSH and shear strength of the joints while it determines the effect of long high-temperature operations on integrity of the soldered joints. It identifies the failure site and mode in the joints and examines failed surfaces to provide information on the morphology of the material microstructure. The results demonstrate that increase in CSH decreases the shear strength of the solder joints and at prolonged operations in high-temperature of about 150 degrees centigrade, solder joint shear strength decreases due to significant formation and growth of brittle intermetallic compound at the interface between substrate pad and solder bulk. EDS analysis shows that this region is characterized by high Tin/Cu content and demonstrates failure mode of crack initiation, propagation and pad lifting.