Kenny C. Otiaba

Thermal interface materials for automotive electronic control unit: Trends, technology and R&D challenges

Abstract The under-hood automotive ambient is harsh and its impact on electronics used in electronic control unit (ECU) assembly is a concern. The introduction of Euro 6 standard (Latest European Union Legislation) leading to increase in power density of power electronics in ECU has even amplified the device thermal challenge. Heat generated within the unit coupled with ambient temperature makes the system reliability susceptible to thermal degradation which ultimately may result in failure. Previous investigations show that the technology of thermal interface materials (TIMs) is a key to achieving good heat conductions within a package and from a package to heat sinking device. With studies suggesting that current TIMs contribute about 60% interfacial thermal resistance, a review of engineering materials has become imperative to identify TIM that could enhance heat transfer. This paper critically reviews the state-of-the-art in TIMs which may be applicable to automotive ECU. Our review shows that carbon-nanotube (CNT) when used as the structure of TIM or TIM filler could considerably advance thermal management issues by improving heat dissipation from the ECU. This search identifies chemical vapor deposition (CVD) as a low cost process for the commercial production of CNTs. In addition, this review further highlights the capability of CVD to grow nanotubes directly on a desired substrate. Other low temperature techniques of growing CNT on sensitive substrates are also presented in this paper.

Fatigue life of lead-free solder thermal interface materials at varying bond line thickness in microelectronics

Microelectronics failure during operation is commonly attributed to ineffective heat management within the system. Hence, reliability of such devices becomes a challenge area. The use of lead-free solders as thermal interface materials to improve the heat conduction between a chip level device and a heat sink is becoming popular due to their promising thermal and mechanical material properties. Finite element modelling was employed in the analysis of the fatigue life of three lead-free solders (SAC105, SAC305, and SAC405) under commercial thermal cycling load (between −40 °C and 85 °C). This paper presents the results of the simulation work focusing on the effect of varying the solder thermal interface thickness (or bond line thickness) on the reliability of the microelectronic device. The results obtained were based on stress, strain, deformation, and plastic work density. The results showed that the fatigue life of the three solders increases as the solder thermal interface thickness increases. Also, the stresses, strains, and deformation were highest around the edges and vertices of the solder interface. In addition, the optimal solder material of choice based on the criteria of this research is given as SAC405. It has higher operational life span and good reliability capabilities.

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

The effect of thermal constriction on heat management in a microelectronic application

Thermal contact constriction between a chip and a heat sink assembly of a microelectronic application is investigated in order to access the thermal performance. The finite element model (FEM) of the electronic device developed using ANSYS software was analysed while the micro-contact and micro-gap thermal resistances were numerically analysed by the use of MATLAB. In addition, the effects of four major factors (contact pressure, micro-hardness, root-mean-squared (RMS) surface roughness, and mean absolute surface slope) on thermal contact resistance were investigated. Two lead-free solders (SAC305 and SAC405) were used as thermal interface materials in this study to bridge the interface created between a chip and a heat sink. The results from this research showed that an increase in three of the factors reduces thermal contact resistance while the reverse is the case for RMS surface roughness. In addition, the use of SAC305 and SAC405 resulted in a temperature drop across the microelectronic device. These results might aid engineers to produce products with less RMS surface roughness thereby improving thermal efficiency of the microelectronic application.

Thermal Management Materials for Electronic Control Unit: Trends, Processing Technology and R and D Challenges

The development of advanced thermal management materials for Electronic Control Unit (ECU) is the key to achieving high reliability and thus safety critical operations in areas of ECU applications such as automotives and power systems. Thermal management issues associated with the operation of ECU at elevated temperature have accounted for some of the recent reliability concerns which have culminated in current systems failures in some automobiles. As the functions of ECU in systems have increased in recent times, the number of components per unit area on its board has also risen. High board density boosts internal heat generated per unit time in ECU ambient. The generated heat induces stress and strain at the chip interconnects due to variation in the Coefficient of Thermal Expansion (CTE) and thermal conductivity of different bonded materials in the assembly. Thermal degradation could become critical and impacts device’s efficiency. The life expectancy of electronic components reduces exponentially as the operating temperature rises thus making thermal management pivotal in electronic system reliability. Since materials’ properties vary with operating condition, material performance has become a major consideration in the design of heat dissipation mechanism in ECU. The development of advanced thermal management materials and hence improving the performance of ECU requires an in-depth understanding of the complex relationship between materials’ properties and their behaviours at elevated temperatures. The paper presents an overview of thermal management materials, review trends in material and processing technology. In addition, the paper outlines the crucial challenges in materials, cost and composite formulations and the outstanding R & D issues.