Sabuj Mallik

Thermal interface materials for automotive electronic control unit: Trends, technology and R&D challenges

Abstract The under-hood automotive ambient is harsh and its impact on electronics used in electronic control unit (ECU) assembly is a concern. The introduction of Euro 6 standard (Latest European Union Legislation) leading to increase in power density of power electronics in ECU has even amplified the device thermal challenge. Heat generated within the unit coupled with ambient temperature makes the system reliability susceptible to thermal degradation which ultimately may result in failure. Previous investigations show that the technology of thermal interface materials (TIMs) is a key to achieving good heat conductions within a package and from a package to heat sinking device. With studies suggesting that current TIMs contribute about 60% interfacial thermal resistance, a review of engineering materials has become imperative to identify TIM that could enhance heat transfer. This paper critically reviews the state-of-the-art in TIMs which may be applicable to automotive ECU. Our review shows that carbon-nanotube (CNT) when used as the structure of TIM or TIM filler could considerably advance thermal management issues by improving heat dissipation from the ECU. This search identifies chemical vapor deposition (CVD) as a low cost process for the commercial production of CNTs. In addition, this review further highlights the capability of CVD to grow nanotubes directly on a desired substrate. Other low temperature techniques of growing CNT on sensitive substrates are also presented in this paper.

Fatigue life of lead-free solder thermal interface materials at varying bond line thickness in microelectronics

Microelectronics failure during operation is commonly attributed to ineffective heat management within the system. Hence, reliability of such devices becomes a challenge area. The use of lead-free solders as thermal interface materials to improve the heat conduction between a chip level device and a heat sink is becoming popular due to their promising thermal and mechanical material properties. Finite element modelling was employed in the analysis of the fatigue life of three lead-free solders (SAC105, SAC305, and SAC405) under commercial thermal cycling load (between −40 °C and 85 °C). This paper presents the results of the simulation work focusing on the effect of varying the solder thermal interface thickness (or bond line thickness) on the reliability of the microelectronic device. The results obtained were based on stress, strain, deformation, and plastic work density. The results showed that the fatigue life of the three solders increases as the solder thermal interface thickness increases. Also, the stresses, strains, and deformation were highest around the edges and vertices of the solder interface. In addition, the optimal solder material of choice based on the criteria of this research is given as SAC405. It has higher operational life span and good reliability capabilities.

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

Solder paste characterisation: towards the development of quality control (QC) tool

Purpose – The purpose of this paper is to develop a quality control tool based on rheological test methods for solder paste and flux media.Design/methodology/approach – The rheological characterisation of solder pastes and flux media was carried out through the creep‐recovery, thixotropy and viscosity test methods. A rheometer with a parallel plate measuring geometry of 40 mm diameter and a gap height of 1 mm was used to characterise the paste and associated flux media.Findings – The results from the study showed that the creep‐recovery test can be used to study the deformation and recovery of the pastes, which can be used to understand the slump behaviour in solder pastes. In addition, the results from the thixotropic and viscosity test were unsuccessful in determining the differences in the rheological flow behaviour in the solder pastes and the flux medium samples.Research limitations/implications – More extensive rheological and printing testing is needed in order to correlate the findings from this s...

Stencil printing behavior of lead-free Sn-3Ag-0.5Cu solder paste for wafer level bumping for Sub-100 μm size solder bumps

Stencil printing for flip chip packaging using fine particle solder pastes is a low cost assembly solution with high throughput for fine pitch solder joint interconnects. The manufacturing challenges associated with both solder paste printing increases as electronic device size decreases due to trend of miniaturization in electronic components. Among multiple parameters, the two most important stencil printing parameters are squeegee pressure and printing speed. In this paper, the printing behavior of Pb free Sn-3Ag-0.5Cu solder paste with a particle size distribution of 2–12 μm for wafer level bumping using a stencil printing method (stencil opening dimension −30 μm) was evaluated by varying the printing speed and squeegee pressure to fabricate solder bumps with a sub 100 μm size. The optimal squeegee pressure and print speed for the defect free printing behavior and fairly uniform size distribution of reflowed paste were found to be 7 kgf and 20 mm/s, respectively. The average size of the reflowed printed paste decreased with the increasing squeegee pressure.

Evaluating solder paste behaviours through rheological test methods and their correlation to the printing performance

Purpose – The purpose of this paper is to study the rheological behaviours of lead‐free solder pastes used for flip‐chip assembly applications and to correlate rheological behaviours with the printing performance.Design/methodology/approach – A range of rheological characterization techniques including viscosity, yield stress, oscillatory and creep‐recovery tests were carried out to investigate the rheological properties and behaviours of four different solder paste formulations based on no‐clean flux composition, with different alloy composition, metal content and particle size. A series of printing tests were also conducted to correlate printing performance.Findings – The results show that in the viscosity test, all solder pastes exhibited a shear thinning behaviour in nature with different highest maximum viscosity. The yield stress test has been used to study the effect of temperature on the flow behaviour of solder pastes. A decrease in yield stress value with temperature was observed. The results fr...

Study of the rheological behaviours of Sn-Ag-Cu solder pastes and their correlation with printing performance

Solder paste plays an important role in the electronic assembly process by providing electrical, mechanical and thermal bonding between the components and the substrate. The rheological characterisation of pastes is an important step in the design and development of new paste formulations. With the ever increasing trend of miniaturisation of electronic products, the study of the rheological properties of solder pastes is becoming an integral part in the R&D of new paste formulations and in the quality monitoring and control during paste manufacture and electronic assembly process. This research work outlines some of the novel techniques which can be successfully used to investigate the rheology of lead-free solder pastes. The report also presents the results of the correlation of rheological properties with solder paste printing performance. Four different solder paste samples (namely paste P1, P2, P3 and P4) with different flux vehicle systems and particle size distributions were investigated in the study. As expected, all the paste samples showed shear thinning behaviour. Although the samples displayed similar flow behaviour at high shear rates, differences were observed at low shear rates. In the stencil printing trials, round deposits showed better results than rectangular deposits in terms of paste heights and aperture filling. Our results demonstrate a good correlation between higher paste viscosity and good printing performance. The results of the oscillatory and thixotropy tests were also successfully correlated to the printing behaviour of solder paste.

A Study of the Rheological Properties of Lead free Solder Paste formulations used for Flip-Chip Interconnection

The market for solder paste materials in the electronics sector is very large and consists of material and equipment suppliers and end users. These materials are used to bond electronic components (e.g. flip-chip, BGA) to printed circuit boards (PCBs) across a range of dimensions where the solder interconnects can be 50 microns to 1 mm in size. For materials suppliers, the trends in the market are towards environmentally friendly materials (e.g. lead-free solders) that can be used at ever-smaller dimension where the properties of the materials must ensure reliable product performance. Equipment suppliers, for example printing machine manufacturers, are continually updating their equipment characteristics to ensure better print yield of solder paste onto a PCB. Whilst the End Users must ensure that the combination of materials and equipment used will provide the required product quality in terms of reliable interconnection performance. This study concerns the rheological characterisation of different lead-free solder paste formulations used for flip-chip interconnections, and is made up of three parts. The first part deals with the measurement of rheological properties with three different measuring geometries, the second part looks into the effect of frequencies on oscillatory stress sweep measurements and the final part reports on the characterisation and comparison of three different lead-free solder paste formulations. The objective of the study is to investigate the rheological behaviour of the three lead-free solder paste formulations used for flip-chip interconnection. Our study shows that of the three plate geometries evaluated, the serrated parallel plate geometry was more effective in minimizing the wall-slip. Our results also show that for the oscillatory stress-sweep measurement, the linear visco-elastic region (LVR) is independent of frequency for the three solder paste formulations. The results also show how wall-slip effects can be minimized in rheological measurements of solder pastes. The paper also outlines how different rheological test methods can be used to characterise solder paste behaviours and useful guide for both paste manufacturers and process engineers implementing flip-chip assembly.

Nonlinear Viscoelastic Characteristics of Sn-Ag-Cu Solder Pastes Used in Electronics Assembly Applications

Sn-Ag-Cu solder pastes are widely used as the joining material in the electronic assembly process. The aim of this work was to evaluate the nonlinear viscoelastic behaviors of three different Sn-Ag-Cu solder pastes. Three novel rheological test methods were developed for this purpose. These include viscosity, thixotropic loop, and oscillatory amplitude sweep tests. The nonlinear flow curves obtained from the viscosity tests revealed the “shear-thinning” behavior of solder paste samples. Thixotropic loop test results explain the time-dependent structural breakdown and recovery of solder pastes. The viscoelastic properties of solder pastes were interpreted through oscillatory test parameters: storage modulus (G′), loss modulus (G″), and phase angle (δ). The discrepancies observed in the rheological behaviors of the paste samples were found to be related with flux composition (liquid phase in the solder paste) and particle size distribution.

Numerical Investigation of Thermo-Mechanical Behaviour of Ball Grid Array Solder Joint at High Temperature Excursion

The solder joints of surface mount components (SMCs) experience thermal degradation culminating in creep and plastic shear strain deformation when subjected to cyclic temperature load over time. Degradation at the joints is due to thermal stress induced by the incompatible, differential and nonlinear expansion mismatch of the different bonded materials in the assembly. The stress magnitude influences the strain behaviour. Plastic strain response of solder joint is critical at the materials interface at the lower part of the joint due to the occurrence of wider variation in the coefficient of thermal expansion of the bonded materials and this may lead to static structural failure. The life expectancy of electronic components reduces exponentially as the operating temperature increases thus making reliability a key concern for electronic systems operating at high temperatures and in harsh environments. This paper reports on the numerical investigation of thermo-mechanical response of a critical BGA joint especially the character of plastic deformation of SnPb solder used in forming the joint as well as the joint’s high temperature reliability. The analysis uses a 3-D models to predict the effect of the transient thermal load on the static structural integrity of a single BGA joint. In this study, the base diameter of solder ball (interface between the PCB, copper pad and the solder) experienced higher damage than the top diameter interconnects. The paper provides a simplified methodology to study the reliability of BGA solder joint at high temperatures excursion.