Emil B. Song

Graphene flash memory.

Graphenes single atomic layer of sp(2) carbon has recently garnered much attention for its potential use in electronic applications. Here, we report a memory application for graphene, which we call graphene flash memory (GFM). GFM has the potential to exceed the performance of current flash memory technology by utilizing the intrinsic properties of graphene, such as high density of states, high work function, and low dimensionality. To this end, we have grown large-area graphene sheets by chemical vapor deposition and integrated them into a floating gate structure. GFM displays a wide memory window of ∼6 V at significantly low program/erase voltages of ±7 V. GFM also shows a long retention time of more than 10 years at room temperature. Additionally, simulations suggest that GFM suffers very little from cell-to-cell interference, potentially enabling scaling down far beyond current state-of-the-art flash memory devices.

Continuity of Graphene on Polycrystalline Copper

The atomic structure of graphene on polycrystalline copper substrates has been studied using scanning tunneling microscopy. The graphene overlayer maintains a continuous pristine atomic structure over atomically flat planes, monatomic steps, edges, and vertices of the copper surface. We find that facets of different identities are overgrown with graphenes perfect carbon honeycomb lattice. Our observations suggest that growth models including a stagnant catalytic surface do not apply to graphene growth on copper. Contrary to current expectations, these results reveal that the growth of macroscopic pristine graphene is not limited by the underlying copper structure.

Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

A 3-D flash memory cell of VRAT (vertical-recess-array-transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (planarized integration on the same plane), which allows for the successful implementation of ultra high density flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.

Robust bi-stable memory operation in single-layer graphene ferroelectric memory

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. V C 2011 American Institute of Physics. [doi:10.1063/1.3619816] Graphene is considered to be an exceptional material with high potential for future electronics, owing to its excellent electronic properties; 1 linear electron energy dispersion, and high room temperature mobility. If feasible, an all graphene-based circuit, including logic, analog, and memory devices, would be of great interest to further extend the performance of current Si-based electronics. Among various device applications, graphene based memory structures are still in their infancy in comparison to its logic and analog applications. To date, graphene memory has been demonstrated through chemical modification, 2 filament-type memristor, 3 nanomechanical switch, 4 and graphene FFETs. 5‐7 In graphene FFETs, however, the ambipolar conduction leads to undesirable on/off states for memory applications. Moreover, the absence of an electronic bandgap and controlled doping makes it difficult to resolve such issues. Therefore, a systematic study of graphene FFET is beneficial to realize graphene-based memory structures. In this Letter, we investigate graphene/PZT FFET structures using exfoliated- and CVD-SLG and their mechanism of operation. We show that exfoliated SLG can be optically identified on a PZT substrate and exhibit a hysteresis of the Vshaped conductance with a large memory window at low operating gate voltages. We compare exfoliated- with CVDSLG FFETs and show that devices made of CVD-SLG exhibit a robust bi-stable current state with a long retention time. In order to construct the SLG FFET, we first engineered a ferroelectric substrate to identify SLG. Previously, we have demonstrated that SLG is invisible under the optical micro

Vertical graphene-base hot-electron transistor.

We demonstrate vertical graphene-base hot-electron transistors (GB-HETs) with a variety of structures and material parameters. Our GB-HETs exhibit a current saturation with a high current on-off ratio (>10(5)), which results from both the vertical transport of hot electrons across the ultrathin graphene base and the filtering of hot electrons through a built-in energy barrier. The influences of the materials and their thicknesses used for the tunneling and filtering barriers on the common-base current gain α are studied. The optimization of the SiO2 thickness and using HfO2 as the filtering barrier significantly improves the common-base current gain α by more than 2 orders of magnitude. The results demonstrate that GB-HETs have a great potential for high-frequency, high-speed, and high-density integrated circuits.

Effect of Spatial Charge Inhomogeneity on 1/f Noise Behavior in Graphene

Scattering mechanisms in graphene are critical to understanding the limits of signal-to-noise ratios of unsuspended graphene devices. Here we present the four-probe low-frequency noise (1/f) characteristics in back-gated single layer graphene (SLG) and bilayer graphene (BLG) samples. Contrary to the expected noise increase with the resistance, the noise for SLG decreases near the Dirac point, possibly due to the effects of the spatial charge inhomogeneity. For BLG, a similar noise reduction near the Dirac point is observed, but with a different gate dependence of its noise behavior. Some possible reasons for the different noise behavior between SLG and BLG are discussed.

A stacked memory device on logic 3D technology for ultra-high-density data storage

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

Suspended few-layer graphene beam electromechanical switch with abrupt on-off characteristics and minimal leakage current

Suspended few-layer graphene beam electro-mechanical switches (SGSs) with 0.15 μm air-gap are fabricated and electrically characterized. The SGS shows an abrupt on/off current characteristics with minimal off current. In conjunction with the narrow air-gap, the outstanding mechanical properties of graphene enable the mechanical switch to operate at a very low pull-in voltage (VPI) of 1.85 V, which is compatible with conventional complimentary metal-oxide-semiconductor (CMOS) circuit requirements. In addition, we show that the pull-in voltage exhibits an inverse dependence on the beam length.

Observation of Single Electron Transport via Multiple Quantum States of a Silicon Quantum Dot at Room Temperature

Single electron transport through multiple quantum levels is realized in a Si quantum-dot device at room-temperature conditions. The energy spacing of more than triple the omnipresent thermal energy is obtained from an extremely small ellipsoidal Si quantum dot, and high charge stability is attained through a construction of the gate-all-around structure. These properties may move us a step closer to practical applications of quantum devices at elevated temperatures. An in-depth analysis on the transport behavior and quantum structure is presented.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material’s work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ∼4.5 V for the Ti-gate device and ∼9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.