Sung-min Kim

Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap

We developed titanium nitride (TiN) based nanoelectromechanical (NEM) switch with the smallest suspension air-gap thickness ever made to date by a “top-down” complementary metal-oxide semiconductor fabrication methods. Cantilever-type NEM switch with a 15-nm-thick suspension air gap and a 35-nm-thick TiN beam was successfully fabricated and characterized. The fabricated cantilever-type NEM switch showed an essentially zero off current, an abrupt switching with less than 3mV/decade, and an on/off current ratio exceeding 105 in air ambient. Also achieved was an endurance of over several hundreds of switching cycles under dc and ac biases in air ambient.

Robust bi-stable memory operation in single-layer graphene ferroelectric memory

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. V C 2011 American Institute of Physics. [doi:10.1063/1.3619816] Graphene is considered to be an exceptional material with high potential for future electronics, owing to its excellent electronic properties; 1 linear electron energy dispersion, and high room temperature mobility. If feasible, an all graphene-based circuit, including logic, analog, and memory devices, would be of great interest to further extend the performance of current Si-based electronics. Among various device applications, graphene based memory structures are still in their infancy in comparison to its logic and analog applications. To date, graphene memory has been demonstrated through chemical modification, 2 filament-type memristor, 3 nanomechanical switch, 4 and graphene FFETs. 5‐7 In graphene FFETs, however, the ambipolar conduction leads to undesirable on/off states for memory applications. Moreover, the absence of an electronic bandgap and controlled doping makes it difficult to resolve such issues. Therefore, a systematic study of graphene FFET is beneficial to realize graphene-based memory structures. In this Letter, we investigate graphene/PZT FFET structures using exfoliated- and CVD-SLG and their mechanism of operation. We show that exfoliated SLG can be optically identified on a PZT substrate and exhibit a hysteresis of the Vshaped conductance with a large memory window at low operating gate voltages. We compare exfoliated- with CVDSLG FFETs and show that devices made of CVD-SLG exhibit a robust bi-stable current state with a long retention time. In order to construct the SLG FFET, we first engineered a ferroelectric substrate to identify SLG. Previously, we have demonstrated that SLG is invisible under the optical micro

A stacked memory device on logic 3D technology for ultra-high-density data storage

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

Suspended few-layer graphene beam electromechanical switch with abrupt on-off characteristics and minimal leakage current

Suspended few-layer graphene beam electro-mechanical switches (SGSs) with 0.15 μm air-gap are fabricated and electrically characterized. The SGS shows an abrupt on/off current characteristics with minimal off current. In conjunction with the narrow air-gap, the outstanding mechanical properties of graphene enable the mechanical switch to operate at a very low pull-in voltage (VPI) of 1.85 V, which is compatible with conventional complimentary metal-oxide-semiconductor (CMOS) circuit requirements. In addition, we show that the pull-in voltage exhibits an inverse dependence on the beam length.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material’s work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ∼4.5 V for the Ti-gate device and ∼9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Back-gate tuning of Schottky barrier height in graphene/zinc-oxide photodiodes

We demonstrate back-gate-tuning of the Schottky barrier height in graphene/zinc oxide photodiodes that are devised by a selective sputter-growth of ZnO on pre-patterned single-layer graphene sheets. The devices show a clear rectifying behavior (e.g., Schottky barrier height ∼0.65 eV and ideality factor ∼1.15) and an improvement in the photo-response via application of a back-gate voltage. The back-gate bias tunes the effective Schottky barrier-height and also promotes the activation of photo-excited carriers, which leads to an enhancement in the thermionic emission process.

Visibility and Raman spectroscopy of mono and bilayer graphene on crystalline silicon

Experimental studies of pristine graphene devices currently rely on the fact that the graphene crystallites can be visible under optical microscopes when the underlying substrate is engineered to exhibit high contrast. Here, we present that graphene can be visualized not only on a dielectric substrate but also on a crystalline Si surface of a silicon-on-insulator (SOI) wafer (SIMOX and Bonded) with thicknesses of Si ∼70 nm and buried oxide ∼140 nm, using monochromatic illumination. In addition, we have found that Raman spectroscopy shows similar features to standard graphene on SiO2 substrates independent of the polarity of the Si surface. Finally, the Raman spectrum on SOI exhibits a higher intensity compared to that on bulk Si due to the interference enhancement effect of graphene on SOI. Thus, the usage of optical microscopy and Raman spectroscopy for detecting, locating, and characterizing graphene serves as a high throughput method to further study graphene on semiconductor systems and other substrat...

Electrical Stress and Total Ionizing Dose Effects on Graphene-Based Non-Volatile Memory Devices

Electrical stress and 10-keV x-ray and 1.8-MeV proton irradiation and annealing responses are evaluated for graphene-based non-volatile memory devices. The memory characteristics of these structures derive primarily from hysteretic charge exchange between the graphene and interface and border traps, similar to the operation of metal-nitride-oxide-semiconductor memory devices. Excellent stability and memory retention are observed for ionizing radiation exposure or constant-voltage stress. Cycling of the memory state leads to a significant reduction in memory window.

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Flexible and Transparent Memory: Non-Volatile Memory Based on Graphene Channel Transistor for Flexible and Transparent Electronics Applications

A Flexible and Transparent charge trap Memory (FTM) based on a single-layer graphene (SLG) channel with a ITO gate electrode was fabricated on a flexible and transparent poly-ethylene naphtalate (PEN) substrate. Triple high-k dielectric stacks Al2O3-AlOx-Al2O3 (AAA) were used as a data storage layer. The FTM shows memory characteristics with a memory window larger than 7V while maintaining ~80% of its transparency in the visible wavelength. The adoption of an AAA gate stack effectively suppressed the electron back injection from the gate electrode. This can be utilized for transparent and flexible electronics that require integration of logic, memory and display on a single flexible substrate with high transparency.