Emilie Bernard

Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

First Internal Spacers' Introduction in Record High

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I_ON/I_OFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance <i>C</i> _gg reduction of 32% is measured, thanks to <i>S</i>-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain <i>A</i> _VI( = <i>gm</i>/<i>g</i> _ds) is improved by 92%.

I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow IOFF (16 pA/mum) and high ION (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher VDsat for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.

Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.

Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4MFP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOI) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 μm diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.