Nathalie Vulliet

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

This paper presents a 50 Gb/s per lane hybrid BiCMOS and silicon photonic integrated circuit for use in fiber optic communications. Fine pitch copper pillars are used to integrate electronics and silicon photonics. The resulting device demonstrates the generation and detection of up to 56 Gb/s NRZ optical signals over 2-km standard single-mode fiber at 1310-nm wavelength. At 40 Gb/s, the link operates error free, and at 56 Gb/s well below KR4 RS-FEC operating BER. The power dissipation of TX including CW laser is 600 mW (450-mW driver, 150-mW CW laser), RX is 150 mW, resulting in total per channel of less than 750 mW.

Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

Low loss 40 Gbit/s silicon modulator based on interleaved junctions and fabricated on 300 mm SOI wafers

We demonstrate high-speed silicon modulators based on carrier depletion in interleaved pn junctions fabricated on 300 mm-SOI wafers using CMOS foundry facilities. 950 µm-long Mach Zehnder (MZ) and ring resonator (RR) modulator with a 100 µm radius, were designed, fabricated and characterized. 40 Gbit/s data transmission has been demonstrated for both devices. The MZ modulator exhibited a high extinction ratio of 7.9 dB with only 4 dB on-chip losses at the operating point.

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires

For the first time, interface properties between high-k and Si or SiGe nanowires (NWs) have been experimentally investigated by adapting charge pumping technique and low-frequency noise measurement. It is found that the interface state density (Dit) of circular Si NWs is ~3 times higher than that of rectangular ones with a deleterious impact on the low field mobility. The oxide trap density in SiGe NWs is otherwise ~3.5 times higher than that of Si NWs which limits the mobility enhancement for this material.

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

For the first time, ultra low I_OFF (16.5 pA/mum) and high I_ONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best I_ON/I_OFF ratios ever reported: 1.4 times 10⁸ (0.8 times 10⁸) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Silicon Photonics R&D and Manufacturing on 300-mm Wafer Platform

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.

Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (Leff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H2 anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

First Internal Spacers' Introduction in Record High

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I_ON/I_OFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance <i>C</i> _gg reduction of 32% is measured, thanks to <i>S</i>-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain <i>A</i> _VI( = <i>gm</i>/<i>g</i> _ds) is improved by 92%.

I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.