Emily Hirsch

Failure Analysis of 1200-V/150-A SiC MOSFET Under Repetitive Pulsed Overcurrent Conditions

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1]. Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as BVDSS, RDS (on), and VGS(th) were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the devices JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications.

Analysis of GaN power MOSFET exporsure to pulsed overcurrents

The advancement of wide bandgap semiconductor materials has led to the development of Gallium Nitride (GaN) power semiconductor devices, specifically GaN Power MOSFETs. GaN devices have improved characteristics in carrier mobility and on-state resistance compared to Silicon solid state switches. With the development of these new power semiconductor devices a need was established to understand the behavior of the devices switching performance under stress, with regards to situations in pulsing circuits. Through the examination of the switching characteristics of GaN devices, the results can be used for the improvement of advanced pulsing circuit design with GaN solid state switches. In this paper the authors develop a test bed to expose the GaN Power MOSFETs to single and repetitive pulsed overcurrents. The test bed was developed using a Pulse Ring Down board in a radially symmetric configuration to minimize the total equivalent inductance and resistance. The test bed switches the GaN MOSFET with low impedance between the DC bus and ground to induce the stress the MOSFET experiences during pulsed overcurrents. The DC characteristics were measured between switching sets to reveal characteristic signs of potential degradation and failure modes due to pulsed overcurrents. The single and repetitive pulse switching characteristics are captured, analyzed, and shown.

An open circuit voltage decay system for performing injection dependent lifetime spectroscopy

Of all of the material parameters associated with a semiconductor, the carrier lifetime is by far the most complex and dynamic, being a function of the dominant recombination mechanism, the equilibrium number of carriers, the perturbations in carriers (e.g., carrier injection), and the temperature, to name the most prominent variables. The carrier lifetime is one of the most important parameters in bipolar devices, greatly affecting conductivity modulation, on-state voltage, and reverse recovery. Carrier lifetime is also a useful metric for device fabrication process control and material quality. As it is such a dynamic quantity, carrier lifetime cannot be quoted in a general range such as mobility; it must be measured. The following describes a stand-alone, wide-injection range open circuit voltage decay system with unique lifetime extraction algorithms. The system is initially used along with various lifetime spectroscopy techniques to extract fundamental recombination parameters from a commercial high-voltage PIN diode.

Simulation and design trade-off analysis of 15 kV SiC SGTO thyristor during extreme pulsed overcurrent conditions

Silicon carbide Super Gate Turn-Off (SGTO) thyristors are an advanced technology for increasing the power density of high voltage pulsed power or power electronic systems. However, the transient characteristics and failure modes of these devices have to be further understood. This paper presents the Atlas TCAD simulation of a 15 kV SiC SGTO thyristor during extreme pulsed overcurrent conditions. The simulated device is first validated against dc measurements of a physical device. The device is then simulated at various pulse current amplitudes using a 10 stage 100 μs PFN. In addition, a tradeoff study for the drift region and anode mesa width is performed.

Evaluation of long term reliability and safe operating area of 15 kV SiC PiN diodes during ultra-high current pulsed conditions

Silicon Carbide (SiC) is a leading wide bandgap semiconductor for increasing the power density of bigb power applications. This paper overviews the long term reliability and safe operating area of15 kV SiC PiN diodes during pulsed current conditions. An automated system is used to stress these devices with ultra-high current pulses and monitor degradation with in-system characterization. The system is capable of a 100 μs full-width half maximum pulse width up to 15 kA, with a repetition rate of 0.5 Hz. Periodic in-system characterization measures device forward conduction and reverse breakdown. The devices in this paper are pulsed at current levels from 1.5 kA to 2.5 kA. Over 100,000 pulses at 1.5 kA have been performed with no degradation. The long term reliability and failure mode results for the 15 kV PiN diodes will be reviewed.

Pulsed power evaluation and simulation of high voltage 4H-SiC P-Type SGTOs

Future Army pulsed power applications semiconductor devices that will meet requirements for high-power, low weight and volume, and fast switching speed. The following paper presents the pulsed power evaluation of high voltage silicon carbide (SiC) super gate turn-off (SGTO) thyristors. These devices are well suited for high voltage, high temperature pulsed power and continuous power electronic systems. A pulse-forming network (PFN) circuit and a low inductance, series resistor-capacitor (LRC) circuit were developed to evaluate both the fast dI/dt capability and the pulse safe operating area (SOA) of the SiC SGTO. Transient simulations of the high voltage SiC SGTOs were also performed on a narrow pulse LRC circuit to investigate the devices switching behavior under extreme pulsed conditions.

Development of secondary breakdown circuit for DV/DT analysis of SIC devices

Silicon carbide (4H-SiC) is a leading option for increasing the power density of pulsed power and power electronic systems1, 2. SiC devices used in high voltage switching applications experience high dV/dt due to fast switching transients. Under high dV/dt conditions the devices can exhibit spurious turn-ON. For SiC devices to achieve widespread acceptance the dV/dt limit must be established. To measure the dV/dt limit, a circuit comprised of four silicon avalanche BJTs operating in secondary breakdown was constructed. This circuit is capable of generating dV/dts well in excess of what SiC unipolar and bipolar devices might be exposed to in typical applications. Two SiC diodes in an “OR” configuration are used to perform a comprehensive dV/dt analysis as a function of dc bias. Using this experimental setup dV/dts up to 200 V/ns were applied to SiC MOSFETs, and the induced gate to source voltage was measured. Preliminary dV/dt results achieved with the secondary breakdown circuit are shown for a range of dc biases.