Emmanuel Rolland

Silicon Technologies for Nanoscale Device Packaging

We present our recent developments on silicon technologies dedicated to the packaging of nano-objects/nano-devices. These technologies aim at both protecting and electrically connecting a nanoscale device positioned on a perfect Si(001)-(2 × 1):H surface smoothed thanks to a 950 °C thermal treatment. The nano-device is connected to nanopads implanted on the silicon surface. Each nanopad is linked to a nanovia which is locally achieved by etching and filling processes operated in a FIB (Focused Ion Beam) equipment. Impacts of the FIB process on via morphology and properties are depicted. Nanopads are fabricated through the local implantation of arsenic, and the effect of the surface smoothing thermal treatment on the dopants diffusion length is estimated by simulation and then experimentally explored. Key process steps such as the etching of a deep cavity and the surface protection with a temporary cap are also described, and a first assembly consisting in a substrate equipped with nanopads and directly bonded with a cap substrate is presented.

CMOS platform for atomic-scale device fabrication

Controlled atomic scale fabrication based on scanning probe patterning or surface assembly typically involves a complex process flow, stringent requirements for an ultra-high vacuum environment, long fabrication times and, consequently, limited throughput and device yield. We demonstrate a device platform that overcomes these limitations by integrating scanning-probe based dopant device fabrication with a CMOS-compatible process flow. Silicon on insulator substrates are used featuring a reconstructed Si(001):H surface that is protected by a capping chip and has pre-implanted contacts ready for scanning tunneling microscope (STM) patterning. Processing in ultra-high vacuum is thereby reduced to a few critical steps. Subsequent reintegration of the samples into the CMOS process flow opens the door to successful application of STM fabricated dopant devices in more complex device architectures. Full functionality of this approach is demonstrated with magnetotransport measurements on degenerately doped STM patterned Si:P nanowires up to room temperature.

Nanopackaging of Si(100)H Wafer for Atomic-Scale Investigations

Ultra-high vacuum (UHV) investigations have demonstrated a successful development of atomic nanostructures. The scanning tunneling microscope (STM) provides surface study at the atomic scale. However, the surface preparation is a crucial experimental step and requires a complex protocol conducted in situ in a UHV chamber. Surface contamination, atomic roughness, and defect density must be controlled in order to ensure the reliability of advanced UHV experiments. Consequently, a packaging for nanoscale devices has been developed in a microelectronic clean room environment enabling the particle density and contaminant concentration control. This nanopackaging solution is proposed in order to obtain a Si(001)-(2×1):H reconstructed surface. This surface is protected by a temporary silicon cap. The nanopackaging process consists in a direct bonding of two passivated silicon surfaces and is followed by a wafer dicing step into 1-cm2 dies. Samples can be stored, shipped, and in situ opened without any additional treatment. A specific procedure has been developed in order to open the nanopackaged samples in a UHV debonder, mounted in the load-lock chamber of a low-temperature STM system (LT-STM). Statistical large scan LT-UHV-SEM images and LT-UHV-STM images have been obtained enabling the surface study at the atomic resolution.

Innovative Solutions for the Nanoscale Packaging of Silicon-Based and Biological Nanowires: Development of a Generic Characterization and Integration Platform

With their attractive intrinsic properties, such as morphology, autoassembling properties, and tailorability, nano-objects could provide alternative and innovative routes to current microelectronics and nanoelectronics. Further insight on their electrical properties, especially in terms of statistics and reproducibility, as well as on their potential integration into silicon-based electronics is, however, often required to be able to fully exploit their potential. This paper proposes an innovative approach using a generic structure allowing the study of nano-objects electrical properties. Regarding the nano-objects integration, a homogeneous approach is presented with the in situ fabrication of atomic wires as a possible planar interconnection system. A heterogeneous approach is described as well with the characterization and preliminary integration of biological material, such as deoxyribonucleic acid-based nanowires or amyloid fibers.