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Featured researches published by Eng Huat Goh.


2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1 | 2003

Effect of Package and Board Pad Size on Optimum Flip Chip Ball Grid Array (FCBGA) Package Thermo-Mechanical Performance

Chee Wai Wong; Cheng Siew Tay; Siew Sang Tan; Vasu Vasudevan; Eng Huat Goh; Shaw Fong Wong

Flip Chip Ball Grid Array (FCBGA) has been a common package technology to achieve higher Input/Output (IO) count. In moving toward higher IO count without increasing the package size, FCBGA package with tighter pitch is required. Unfortunately, ball pitch reduction from 1.27mm to 1mm in FCBGA packages is not a transparent change. Instead, it provides an inside into the thermo-mechanical performance of FCBGA solder joint. Previous study indicated the importance of the package solder resist opening-to-board pad size ratio (AR) as the dominant factor in improving the thermo-mechanical performance of the solder joint at one solder system. An optimum range of AR had been defined as failure free zone with respect to the temperature cycling stress from −40degC to 85degC. This paper is a continued study, which focused on identifying the optimum range of AR for failure free zone. Key factors under the study are package solder resist opening (SRO), die size, population pattern, type of board pad, type of package design and thermal solution. This paper consolidates the modeling and empirical data on the relationship. The results of the study has brought towards an identification of process window for 1mm pitch FCBGA package and led to package and board design rules in terms of targeted SRO & board pad size, type of pad design and a tightening of SRO & board pad size specification. Besides, the learning has led towards a new look into the BGA package certification in which SRO and board pad size are key factors in the design consideration.Copyright


Archive | 2007

Interconnects with interlocks

Jiun Hann Sir; Eng Huat Goh


Archive | 2012

MICROELECTRONIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS

Eng Huat Goh; Hoay Tien Teoh


Archive | 2018

INTERPOSEURS DE FOND DE BOÎTIER POUR DISPOSITIFS CONFIGURÉS CÔTÉ PASTILLE POUR APPAREIL DE TYPE SYSTÈME EN BOÎTIER

Howe Yin Loo; Eng Huat Goh; Min Suet Lim; Bok Eng Cheah; Jackson Chung Peng Kong; Khang Choong Yong


Archive | 2018

TECHNOLOGIE "PACKAGE ON PACKAGE" (POP) POUR DISPOSITIFS ÉLECTRONIQUES

Eng Huat Goh; Jiun Hann Sir; Min Suet Lim; Xi Guo


Archive | 2018

Integrated circuit package substrate with microstrip architecture and electrically grounded surface conductive layer

Eng Huat Goh; Min Suet Lim; Sir Jiun Hann; Seok Ling Lim; Hoay Tien Teoh


Archive | 2017

FLEXIBLE PRINTED CIRCUIT EMI ENCLOSURE

Khang Choong Yong; Stephen H. Hall; Tin Poay Chuah; Boon Ping Koh; Eng Huat Goh


Archive | 2017

BOARD-EDGE INTERCONNECTION MODULE WITH INTEGRATED CAPACITIVE COUPLING FOR ENABLING ULTRA-MOBILE COMPUTING DEVICES

Jackson Chung Peng Kong; Eng Huat Goh; Bok Eng Cheah; Su Sin Florence Phun; Khang Choong Yong; Min Keen Tang


Archive | 2017

FPC CONNECTOR FOR BETTER SIGNAL INTEGRITY AND DESIGN COMPACTION

Eng Huat Goh; Hoay Tien Teoh


Archive | 2017

SUBSTRATE INCLUDING STRUCTURES TO COUPLE A CAPACITOR TO A PACKAGED DEVICE AND METHOD OF MAKING SAME

Tin Poay Chuah; Min Suet Lim; Ping Ping Ooi; Eng Huat Goh; See Chin Chow

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