Khang Choong Yong

Signaling analysis of inter-chip I/O package routing for Multi-Chip Package

Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs [1]. However, the high density interchip I/O routing within package presents unique signaling challenges when coupled with high operating data rate. This paper focuses on the signaling analysis of the inter-chip I/O package routing between silicon devices in MCP. In this study, high level signal quality and eye margin sensitivity were evaluated from 2.5GHz up-to 7.5GHz. The microwave effect is found dominating the transmission line component that resulted in signal quality deteriorations. Key limiting factors such as crosstalk coupling effects, signal reflections and frequency dependent losses that caused signal quality degradations were identified and categorized according to the operating frequency and channel length for future MCP design considerations.

Crosstalk study of high speed on-package interconnects for multi-chip package

This paper presents the crosstalk analysis study for high-speed on-package interconnects in multi-chip package (MCP). The crosstalk coupling effects from adjacent aggressors on signaling performance e.g. eye opening and signal overshoot were investigated in this study. Simulations were performed on both microstrip and stripline structures from 2Gbps up-to 6Gbps. Several key design parameters e.g. package trace width and trace spacing ratio as well as the channel length were further explored to identify the dominating factor of crosstalk coupling in the high-speed on-package interconnect design. Simulation results indicated the crosstalk effects from adjacent aggressors beyond second order still have significant impacts on the signaling performance and need to be carefully considered for high-speed MCP applications. This paper also establishes several guidelines to enable optimum design trade-off between signaling performance and silicon real-estate.

A novel trench routing for next-generation high-speed serial buses beyond 10Gbps applications

This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect channel loss budget as stipulated by standard development body e.g. USB-IF specifications. This inventive routing provides huge benefit to original equipment manufacturer (OEM) in term of platform component removal (e.g. USB 3.1 re-timer that costs ∼

3D Interconnects — The enabler of next generation multi-Gbps single-ended bus

1) for high-speed differential links >10Gbps data transfer rates. These cost-adding repeaters would be indispensable under conventional routing for instance microstrip, stripline and dual-stripline for high-speed applications. The PCB trench routing aims to mitigate the existing and future challenges of next-gen multi-Gbps signaling, of which one of the platform length limitations is PCB interconnect loss. In this work, signaling analysis in 10Gbps USB 3.1 and 32Gbps SerDes applications have shown feasibility of yielding significant eye margin improvements i.e. up-to 30% voltage margin improvements, which also translates into ample board design flexibility with extended platform routing length.

Signaling scheme for high speed die-to-die interconnection in multi-chip package (MCP) technology

The rising demands of miniaturize and high performance electronic gadgets necessitates higher density with higher bandwidth interconnect which is being limited by prevailing microwave effects as signaling data-rate surges and routing pitch shrinks. This paper presents a transmission line design with three-dimentional (3D) reference plane to alleviate the signaling crosstalk impacts that limit the performance scaling of high-speed parallel bus design such as on-package interconnects (OPI). Simulation result indicates eye opening improvements of >40% for OPI bus operates at 4Gbps data rate is feasibible with the crosstalk reduction achieved through the 3D reference plane design.

APPARATUS AND METHOD FOR ADAPTIVE COMMON MODE NOISE DECOMPOSITION AND TUNING

Multi-chip package (MCP) technology has recently advanced as an alternative packaging solution to enable high performance and power-efficient mobile electronic devices. The wide adoptions of MCP technology are mainly driven by reduced circuit complexity, heterogeneous integration across different silicon process technology and shorter product cycle time. However, the high density on-package die-to-die (D2D) interconnects within package presents unique signaling challenges as the operating frequency continue to rise. This paper analyzes various low power passive signaling enhancement techniques e.g. equalization and termination to mitigate the signal integrity challenges of the high speed on-package D2D channels. The effectiveness of various signaling enhancement techniques and topologies were studied and compared in terms of eye opening and overshoot performances. The combination of series-source termination and parallel-load termination was found to be a feasible candidate in view of optimum trade-off between performance and silicon real-estate or costs. Simulation results show the recommended topology is able to achieve 300mV/40ps eye opening at 15Gbps.