Enrico Sacchi

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver

This paper describes a fully integrated low noise amplifier (LNA) + mixer + first filtering stage, suitable for direct conversion receivers. Its key feature is a current driven passive mixer loaded by a low impedance. Measurements performed on a 0.18 /spl mu/m CMOS prototype, confirm that this architecture, when compared to a classic one, gives a much smaller flicker noise (70 kHz 1/f corner), together with an excellent noise figure (4.4 dB integrated from 10 kHz to 1.92 MHz), while requiring only 15 mW of power. Moreover, a very good linearity is simultaneously achieved (IIP3=-1 dBm). The main limitation of the present implementation is the bandwidth of the opamp that implements the mixer load. Due to this, IIP3 degrades at higher frequencies (IIP3 about -12 dBm at 10 MHz). This is however not a fundamental limitation.

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the authors knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.

Measurement and modeling of Si integrated inductors

This work describes a method to derive from measurements an accurate lumped element model of spiral integrated inductors on silicon substrate. The analysis method is based on a wideband two-port measurement of the s-parameters of the device under test and enables an accurate evaluation of the parasitic effects that limit the performances of these integrated devices.

An innovative modelization of loss mechanism in silicon integrated inductors

In this paper, we present an improved lumped-element equivalent circuit of silicon integrated inductors, which accurately takes into account parasitic effects and separately models the effect of metal and substrate losses. We describe an efficient procedure to deduce all the elements of the equivalent circuit from wideband, two-port measurements of the S-parameters of the inductor. The separate characterization of metal and substrate losses allows us to evaluate separately their contribution to the inductors Q-factor. We also report the results of the characterization of some CMOS and BiCMOS integrated inductors designed to be included in radio frequency integrated circuits operating at 1.8 GHz.

A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA

A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.

An LTE transmitter using a class-A/B power mixer

For an LTE transceiver it is quite challenging to reduce power and area while preserving performance. For large emitted signals the TX dominates power consumption but in the past this situation was sufficiently infrequent not to affect energy consumption. In recent times the statistical distribution of the TX power has shifted upward due to the use of data-intensive communications and the introduction of multi-gain power amplifiers. Therefore to extend battery life in fourth generation terminals, TX consumption at high power (>-10dBm) should be reduced. A second challenge of an FDD LTE TX is noise and distortion emission in the RX band since the TX-to-RX distance, relative to the channel bandwidth, can be much smaller than in previous standards [1].

Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at

In this paper, we analyze the potentials of a four-phase 14-GHz CMOS voltage-controlled oscillator, tailored to a sub-harmonic receiver, for signal processing at Ka-band. When mild phase accuracies between in-phase and quadrature down-converted signals are required, the four-phase oscillator displays roughly the same phase noise figure-of-merit as quadrature oscillator counterparts. However, the operation at half-frequency leads to an improved performance due to a higher quality factor of the tuning varactors, and because the local oscillator circuitry and signal path run at different frequencies, relaxing coupling issues. A detailed time-variant analysis of phase noise in multiphase oscillators is introduced and validated by both simulations and experiments. Prototypes realized in a 65-nm technology occupy an active area of 0.5 mm2 and show the following performances: a 26% frequency tuning range (from 12.2 to 15.9 GHz), maximum phase error from pi/4 of 2deg, and a phase noise of -110 dBc/Hz at 1 MHz from 14 GHz, while consuming 18 mA from 0.8-V supply.

Ka

A 1.55GHz CMOS RF transmitter with an integrated class-C power amplifier (PA) is described. The transmitter uses Cartesian feedback to meet EDGE linearity requirements and integrates a direct-conversion modulator, PA, LO phase shifter, feedback mixers and baseband loop filter in a 0.18mum CMOS process. The transmitter produces an 18dBm EDGE modulated output with 18% drain efficiency

-Band

This paper presents an improved lumped-element equivalent circuit of silicon integrated inductors, that accurately describes the effect on the Q-factor of the electromagnetic coupling between the metal strips and the substrate. In the proposed model a magnetic coupling describes the interaction between the substrate and the spirals of metal. The equivalent circuit is extracted using a characterization procedure that, from two-port wide-band measurement of the S-parameters, automatically yields the value of the lumped-element via the method of least square minima.