Guido Albasini

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm

A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning

A quadrature oscillator employs a transformer-capacitor network as an energy tank. Frequency tuning is done by varying the transformer magnetic field via the ratio of currents in the two windings. Realized prototypes have a 3.2 to 7.3GHz frequency tuning range, a phase noise FOM of 176.5dB at 3.2GHz, 170.5dB at 6.4GHz, and 164dB at 7GHz, all calculated at 10MHz offset, and a phase error of <1.5deg

An UMTS /spl Sigma//spl Delta/ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques

This paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 /spl mu/m CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9/spl times/1.6 mm/sup 2/) 2.1 GHz /spl Sigma//spl Delta/ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth.

A multi-standard WLAN RF front-end transmitter with single-spiral dual-resonant tank loads

This paper describes a radio frequency (RF) front end transmitter for wireless LAN (WLAN), designed for the most common standards, integrated in digital CMOS 0.18mum technology. It covers 802.11a/b/g specifications, concurrently working in the 2.5GHz and 5-6GHz frequency ranges. An innovative solution for the design of the LC tank allows to use a single-spiral inductor in dual resonant tank, with a strong reduction in die area. The dual band RF transmitter size is only 1mm, the smallest ever reported in literature

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of

A 0.2–11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS

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65 nm CMOS SSB mixer for UWB synthesiser

/4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The stand-alone ILRO demonstrates 0.2–11.7 GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and −40 °C to +120 °C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7-bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2–11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser With 35Hz Frequency Step and Quantization Noise Compensation

An injection-locked ring oscillator (ILRO) leveraging mixed analog/digital calibration loops for high-accuracy 8-phase clock generation is proposed. A phase detector (PD) based on passive mixers measures the quadrature error and continuously tunes the oscillator for fine phase correction. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. The ILRO maintains high phase accuracy over a wide operation frequency range and large supply and temperature variations. The chip is fabricated in 28nm FDSOI CMOS and with power consumption from 3mW to 15mW, measurements demonstrate a 0.2-11.7GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and -40×120°C temperature variations. Measured performances meet the requirements of 1-to-45Gb/s quarter-rate multi-standard I/O receivers.