Ivan Bietti

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver

This paper describes a fully integrated low noise amplifier (LNA) + mixer + first filtering stage, suitable for direct conversion receivers. Its key feature is a current driven passive mixer loaded by a low impedance. Measurements performed on a 0.18 /spl mu/m CMOS prototype, confirm that this architecture, when compared to a classic one, gives a much smaller flicker noise (70 kHz 1/f corner), together with an excellent noise figure (4.4 dB integrated from 10 kHz to 1.92 MHz), while requiring only 15 mW of power. Moreover, a very good linearity is simultaneously achieved (IIP3=-1 dBm). The main limitation of the present implementation is the bandwidth of the opamp that implements the mixer load. Due to this, IIP3 degrades at higher frequencies (IIP3 about -12 dBm at 10 MHz). This is however not a fundamental limitation.

A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization

A seventh-order phase equiripple continuous time filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read channel applications is presented. The 7-50 MHz cutoff frequency, amount of boost, and group-delay slope are programmable via 7-b digital-to-analog converters (DACs). At 50 MHz fc, power consumption is 70 mW and output swing for 1% distortion is more than 500 mVpp. The transconductance capacitance (Gm-C) filter is built in a 0.7-/spl mu/m 10-GHz BiCMOS technology.

High-frequency analog filters in deep-submicron CMOS technology

High-frequency analog filters are used in two areas. First, as preprocessing blocks in front of an A/D or as post processing blocks after a D/A. Examples are anti-alias filters for digital TVs, equalizers in digital modems and preconditioning filters in data recording channels (HDD). Second, as building blocks in the front end of a /spl Sigma//spl Delta/ converter. This paper concentrates on submicron CMOS continuous-time filters since increasing system speed requires use of the latest IC technology.

A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA

A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.

Experimental study and modeling of the white noise sources in submicron Pand N-MOSFETs

This paper presents the results of the experimental characterization of the channel thermal noise in MOSFETs belonging to a submicron gate process, with minimum gate length L=0.35 /spl mu/m. The data are compared with a noise model taking into account short-channel effects such as velocity saturation and hot carriers. The contribution of gate and substrate parasitic resistors is also evaluated and included in the model. The analysis is carried out for devices with various gate geometries, investigating the behavior of the noise-related parameters in the range of small gate-to-source overdrive voltages, which is of major concern for low-power circuits.

A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter

A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mW

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm

An UMTS /spl Sigma//spl Delta/ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques

This paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 /spl mu/m CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9/spl times/1.6 mm/sup 2/) 2.1 GHz /spl Sigma//spl Delta/ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth.