Samuel Pagliarini

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

This paper proposes a soft error characterization methodology to analyze multiple faults caused by single-event-induced charge sharing in standard-cell based ASIC designs. Fault injection campaigns have been executed using data provided by placement analysis as well as a pulse width modeling through electrical simulation. Experimental results demonstrate that the error rate can be largely overestimated if placement is not considered.

Exploring the Limitations of Software-based Techniques in SEE Fault Coverage

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults.

Constrained placement methodology for reducing SER under single-event-induced charge sharing effects

This paper presents a methodology to reduce the impact of double faults in a circuit by constraining the placement of its standard cells. A fault-injection emulation platform is used to analyze the single-event-induced charge sharing effect in every pair of nodes. Based on the sensitivity of each pair, guidelines are set in a commercial standard cell placement by using constraints. Results show that by correctly choosing the nodes location, the error rate resulting from double faults can be reduced compared to single fault.

A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware

This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor-based systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime. When combined with fault tolerance techniques based on software, this solution offers full system protection against transient faults. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. HW/SW implementation in a reprogrammable platform shows smaller memory area and execution time overhead when compared to related works. Fault injection results show the efficiency of this method by detecting 100% of faults.

Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique

This paper presents a non-intrusive hybrid fault detection mechanism based on reconfigurable architectures and software-based techniques to detect transient effect faults in microprocessors. These types of faults have a major influence in microprocessors, affecting both data and control flow. In order to protect the system, an on-line checker module is automatically generated, based on the application that is running on the microprocessor, and reconfigured during runtime, in order to spoof the data exchanged between the microprocessor and its memory and to verify the applications consistency. When combined with fault tolerance software-based techniques, this solution offers full system protection against control flow errors, while allowing developers to add further software-based techniques to protect the system against data flow errors. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

Evaluating coverage collection using the VEasy functional verification tool suite

This paper describes a performance evaluation of coverage collection on different simulators. It also describes how coverage is collected using VEasy, a tool suite developed specifically for aiding the process of Functional Verification. A Verilog module is used as an example of where each coverage metric applies. The block and toggle coverage collection algorithms used in VEasy are presented and explained in detail. Finally, the results show that the algorithms used in VEasy are capable of performing coverage collection with a lower simulation overhead when compared with commercial simulators.

VEasy: A tool suite for teaching VLSI functional verification

This paper describes a tool suite aimed at Functional Verification (FV) teaching in the context of VLSI circuits. FV is considered a major bottleneck in design cycles and one of the reasons is the lack of proper training. Therefore teaching it at the undergraduate or graduate levels is an important issue. This paper presents VEasy and describes the features that allow for lint analysis, simulation, data generation by a Graphical User Interface, checking and coverage collection and analysis. All these features merge together to create a complete verification environment, which is appropriated for teaching several concepts of FV.

Non-intrusive reconfigurable HW/SW fault tolerance approach to detect transient faults in microprocessor systems

This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime. When combined with fault tolerance techniques based on software, this solution offers full system protection against transient faults. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. HW/SW implementation in a reprogrammable platform shows minimal memory area and execution time overhead. Fault injection results show the efficiency of this method on detecting 100% of faults.