Eric M. Panning

Implementing flare compensation for EUV masks through localized mask CD resizing

Early production EUV exposure tools may have difficulty achieving flare requirements in the 5-6% range for the 32nm technology node. In this case, flare compensation may be needed to achieve the necessary CD control budget for production. This paper explores both experimentally as well as computationally wafer CD compensation though mask CD resizing so that proper CD control across the exposure field can be maintained. Experimental resist data collected on POB#2 of the Engineering Test Stand (ETS) suggest that even a simple linear CD compensation model can signifantly improve CD contorl in the presence of flare variation. Extending a similar concpet to a hypothetical full-field 25×33 mm2 mask area containgin 20 nm gate CDs shwos taht CD compensation, while computationally demanding, can be realized through a convolution approach of a 1×1 mm2 mask area using a non-uniform adaptive grid.

One small step: world's first integrated EUVL process line

The Intel lithography roadmap calls for Extreme Ultraviolet Lithography (EUVL) to be used for the 32 nm node. With the installation of the EUV Micro-Exposure Tool (MET) complete, Intel now has the worlds first integrated EUVL process line including the first commercial EUV exposure tool. This process line will be used to develop the EUV technology, including mask and resist, and to investigate issues such as defect printability. It also provides a test-bed to discover and resolve problems associated with using this novel technology in a fab (not lab) environment. Over 22,000 fields have been exposed, the discharge-produced plasma light source has operated for 50,000,000 pulses, 8 masks have been fabricated, and 8 resists have been characterized. The MET combines high resolution capability with Intels advanced processing facilities to prepare EUVL for high-volume manufacturing (HVM). In this paper we review the MET installation and facilities, novel capabilities of the linked track, data on optics quality and modeled tool capability, and the MET mask fabrication process. We present data on tool performance including printing 45 nm 1/2 pitch lines with 160 nm depth of focus and 27 nm isolated lines. We show tool accuracy and repeatability data, and discuss issues uncovered during installation and use.

Determination of the flare specification and methods to meet the CD control requirements for the 32-nm node using EUVL

The minimum gate CD for the 32 nm node is 15 nm and the CD control requirement on the gate CD is < 2.5 nm 3σ. One of the major concerns for meeting these targets using EUV lithography is flare. Flare degrades the aerial image contrast which decreases the process window, and within-die chrome density variation results in local flare variation which worsens the CD control. Since mirror roughness contributes to flare, mirror polishing needs to be improved so that the Mid Spatial Frequency Roughness (MSFR) will be reduced to < 0.14 nm/mirror for 6 mirror imaging systems. In this paper, we will determine the minimum acceptable flare for the 32 nm node to meet the CD target and control requirements using modeling and present methods to meet them as demonstrated by experiments run on the Engineering Test Stand (ETS). Effectiveness of flare mitigation methods using chrome dummification and negative tone resists are quantified, and the capability of Flare Variation Compensation (FVC) to meet CD control targets are verified experimentally.

Initial results from the EUV engineering test stand

The Engineering Test Stand (ETS) is an EUV lithography tool designed to demonstrate full-field EUV imaging and provide data required to accelerate production-tool development. Early lithographic results and progress on continuing functional upgrades are presented and discussed. In the ETS a source of 13.4 nm radiation is provided by a laser plasma source in which a Nd:YAG laser beam is focused onto a xenon- cluster target. A condenser system, comprised of multilayer-coated and grazing incidence mirrors, collects the EUV radiation and directs it onto a reflecting reticle. The resulting EUV illumination at the reticle and pupil has been measured and meets requirements for acquisition of first images. Tool setup experiments have been completed using a developmental projection system with (lambda) /14 wavefront error (WFE), while the assembly and alignment of the final projection system with (lambda) /24 WFE progresses in parallel. These experiments included identification of best focus at the central field point and characterization of imaging performance in static imaging mode. A small amount of astigmatism was observed and corrected in situ, as is routinely done in advanced optical lithographic tools. Pitch and roll corrections were made to achieve focus throughout the arc-shaped field of view. Scan parameters were identified by printing dense features with varying amounts of magnification and skew correction. Through-focus scanned imaging results, showing 100 nm isolated and dense features, will be presented. Phase 2 implementation goals for the ETS will also be discussed.

Comparison of techniques to measure the point spread function due to scatter and flare in EUV lithography systems

The source of flare in EUVL systems is mostly from the mid-spatial frequency roughness (1 /μm - 1 /mm spatial periods) of mirrors. Due to the challenges in polishing mirrors to a small fraction of the wavelength, flare in EUV lithography tools is expected to be greater than flare in current DUV tools. Even though EUV flare is constant across the field, there can be within-die flare variations due to variations in layout density. Hence, it is expected that to meet the CD control requirements for the 32 nm node, Flare Variation Compensation (FVC), akin to Optical Proximity Correction (OPC) would be required. FVC needs the within-die flare level estimated by convolving the Point Spread Function due to scatter (PSFsc) with the mask layout. Thus, accurate knowledge of the system PSFsc is essential for FVC. Experimental results of the Modulation Transfer Function (MTF) technique to estimate flare and the PSFsc of the Engineering Test Stand (ETS) are presented. It was also determined that due to the nature of the PSFsc in EUVL tools a more accurate measure for flare would be to use the 0.5 μm line as opposed to the current 2 μm line standard for measuring flare on DUVL tools.

Lithographic characterization of improved projection optics in the EUVL engineering test stand

Static and scanned images of 100nm dense features for a developmental set of l/14 optics (projection optics box # 1, POB 1) in the Engineering Test Stand (ETS) were successfully obtained with various LPP source powers last year. The ETS with POB1 has been used to understand initial system performance and lithographic learning. Since then, numerous system upgrades have been made to improve ETS lithographic performance to meet or exceed the original design objectives. The most important upgrade is the replacement of POB 1 with an improved projection optics system, POB2, having lower figure error (l/20 rms wavefront error) and lower flare. Both projection optics boxes are a four-mirror design with a 0.1 numerical aperture. Scanned 70-nm dense features have been successfully printed using POB2. Aerial image contrast measurements have been made using the resist clearing method. The results are in good agreement to previous POB2 aerial image contrast measurements at the subfield exposure station (SES) at Lawrence Berkeley National Laboratory. For small features the results deviate from the modeling predictions due to the inherent resolution limit of the resist. The intrinsic flare of POB2 was also characterized. The experimental results were in excellent agreement with modeling predictions. As predicted, the flare in POB2 is less than 20% for 2μm features, which is two times lower than the flare in POB1. EUV flare is much easier to compensate for than its DUV counterpart due to its greater degree of uniformity and predictability. The lithographic learning obtained from the ETS will be used in the development of EUV High Volume Manufacturing tools. This paper describes the ETS tool ETS tool setup, both static and scanned, that was required after the installation of POB2. The paper will also describe the lithographic characterization of POB2 in the ETS and cmpare those results to the lithographic results obtained last year with POB1.

Intel's EUV resist development

The success of extreme ultraviolet (EUV) lithography depends upon developing resists that meet the patterning requirements for the technology node in which EUV is inserted. This paper presents Intel’s patterning requirements and development strategies for EUV resists. Two of the primary problems for EUV resists are meeting the linewidth roughness (LWR) requirement, and reducing resist absorbance to obtain good sidewall profiles. Benchmarking data shows that none of the current EUV photoresists meet LWR targets. Modeling results for EUV resists show the impact of resist absorbance on sidewall angle and resolution.

Lithographic evaluation of the EUV engineering test stand

Static and scanned images of 100 nm dense features were successfully obtained with a developmental set of projection optics and a 500W drive laser laser-produced-plasma (LPP) source in the Engineering Test Stand (ETS). The ETS, configured with POB1, has been used to understand system performance and acquire lithographic learning which will be used in the development of EUV high volume manufacturing tools. The printed static images for dense features below 100 nm with the improved LPP source are comparable to those obtained with the low power LPP source, while the exposure time was decreased by more than 30x. Image quality comparisons between the static and scanned images with the improved LPP source are also presented. Lithographic evaluation of the ETS includes flare and contrast measurements. By using a resist clearing method, the flare and aerial image contrast of POB1 have been measured, and the results have been compared to analytical calculations and computer simulations.

EUV mask infrastructure readiness and gaps for TD and HVM

The industry is transitioning EUV lithography from feasibility phase to technology development. EUV mask infrastructure needs to be prepared to support the technology development and ready to enable the implementation of EUV lithography for production. In this paper, we review the current status and assess the readiness of key infrastructure modules in EUV mask fabrication, inspection and control, and usage in a mask cycle: blank quality and inspection, pattern inspection, defect disposition and repair, pellicle integration, and handling of pelliclized masks.

Current status of 157-nm mask technology development

157-nm lithography has gained significant momentum and worldwide support as the post-193 nm technology. Due to higher absorption at shorter wavelength, however, there are several critical issues including materials and reticle handling at 157-nm. These key technical areas are being studied at Intel in collaboration with worldwide industrial and academic partners. In this paper, we will report the progress on 157-nm specific mask technology development.