Muhammad Abdullah Khan

Analysis and design of an unconditionally stable common-drain class-B RF power amplifier in 90 nm CMOS technology

Modern communication networks demand power amplifiers (PAs) which are efficient and have low distortion. The common drain amplifier has the potential to become a linear amplifier with good efficiency, when biased at or above class-B. The main challenge is to provide unconditional stability while still maintaining adequate transducer gain so that the power added efficiency (PAE) will not be compromised by low gain and, thus, resulting in better overall performance. In this contribution, analysis and design of an unconditionally stable common drain class-B PA for the LTE band at 2.55 GHz in 90 nm CMOS is presented. The simulation results show that the designed PA can deliver an output power of more than 27.2 dBm with gain of 6.1 dB and PAE greater than 43.0 % when operated from 2.5 V supply. The circuit has a third order intermodulation distrotion suppression of 32.0 dBc at 3 dB input back-off.

2.6 Class-0: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications

Integration of RF transceiver blocks along with the digital signal processing part in CMOS is becoming the trend in the semiconductor industry for lower cost and smaller form factor. Nowadays, the interest is even growing towards implementing the RF PA in CMOS technology. Cost reduction, diversifying means of fabrication and the addition of performance enhancement circuitry are the main reasons behind this growing interest. However, implementing RF PAs for 3G/4G standards in CMOS is quite challenging: The low breakdown voltage of nanoscale CMOS causes a ruggedness problem at typical average output power (Pavg) levels of 26dBm or more. In the paper, power-combining techniques were used to reach PA output power (Pout) of 33dBm. However, amplification of signals with high peak-to-average-power-ratio (PAPR) requires also a high degree of linearity. Significant AM-PM distortions caused by the voltage-dependent parasitics are a fundamental problem in CMOS PAs. Thus far, predistortion is used to meet EVM requirements. To overcome these challenges, this work presents a new class of operation, termed as Class-O, demonstrated by the design and the measurement of a single-stage PA implemented in 0.13μm CMOS and operating from a 3.3V supply.

Study on load transformation networks for differential common drain class-B RF power amplifier

Common drain class-B PAs have the potential of providing high linearity and efficiency. This work analyses the performance of differential common drain class-B power amplifiers (PAs) in terms of linearity, efficiency and time-domain waveforms depending on the load transformation network (LTN) used. Four different LTNs, which provide the required impedance conditions for class-B operation are analysed and the circuit performance of common drain PAs is verified and compared in simulations. The transformer based LTN shows maximum linearity due to the high degree of symmetry. Third-order intermodulation distortion, IMD3 at 3 dB output power back-off from 1 dB compression point, P1dB is 36 dBc while second harmonic rejection is 103 dBc at an input power of 20 dBm. Peak power added efficiency, PAE of 40.6 % was achieved with this configuration. An equivalent off-chip load network achieves peak PAE of 30 % with IMD3 rejection of 31 dBc at 3 dB back-off from P1dB and second harmonic rejection of 24.7 dBc for an input power of 20 dBm. A compromise between area and integration complexity can be obtained with the other two designs analysed. The results confirm that differential common drain class-B PAs have the potential of providing good linearity also for modern digitally modulated signals.

Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications

This paper presents a highly linear low-band 706MHz LTE compatible class-O RF power amplifier in 130nm CMOS technology for handheld wireless applications. Class-O topology uses a combination of common-source and common-drain amplifiers working in parallel with high linearity without the need for digital predistortion(DPD). With continuous wave measurements, 1-dB compression point (P1dB) of 30.6dBm and peak power added efficiency (PAE) of 45.2% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an ACPR less than -30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common-source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst VSWR conditions.

Highly linear 1.6 GHz 3.3V RF power amplifier using floating body technique in triple-well 130 nm CMOS technology

Power amplifiers (PAs) in CMOS technology have drawn considerable interest for meeting 4th generation (4 G) wireless standards due to their low cost and high level of integration. At increasing power levels, (around 1 W), it becomes challenging to meet the linearity constraints. In this paper, we investigate a differential common source class-AB RF PA employing floating body and compare it with a body-source shorted version. We use triple-well NMOS RF devices at 1.6 GHz in 130nm CMOS technology. Linearity is improved for the floating body based amplifier in terms of AM/PM and 3rd order intermodulation (IMD3) suppression by 1.8° and 1.5 dBc at P1dB as compared to a body-source shorted amplifier. The linearity is evident over all output power (Pout) levels. The linear gain is reduced by 0.42 dB due to increased coupling between drain and source terminals while the PAE is increased by 1.6% at P1dB for floating body based amplifier.

Class-O power amplifier with enhanced linearity using floating body technique in 130 nm standard CMOS technology

In this paper, we present a modified class-O power amplifier (PA) which employs floating-body technique to achieve high linearity. Class-O is a new PA topology which incorporates two sub-amplifiers working in parallel to achieve high linearity and efficiency. The two sub-amplifiers are operated in common drain (CD) and common source (CS) configuration. The proposed floating-body technique is verified with on-wafer measurements on single power transistors. The simulation results of overall class-O amplifier show a 2.3 dB improvement in output 1 dB compression point (Pout1dB) over the conventional body shorted to source version of the amplifier. The power added efficiency (PAE) of proposed class-O is 33.3% as compared to 24% for conventional version. Hence, enabling the proposed amplifier to transmit higher linear output power with more efficiency. The operating frequency of both the amplifiers 960MHz and the technology used is UMC 130nm standard RFCMOS.

A four-channel GNSS front-end IC for a compact interference- and jamming-robust multi-antenna Galileo/GPS receiver

We present a four-channel GNSS front-end IC for a compact interference- and jammer-robust multi-antenna sub-sampling receiver for Galileo El-B/C and GPS LI signals. The front end includes four coherent RF-to-IF signal paths with an intermediate frequency of 75.42 MHz, a common PLL frequency synthesizer, which generates the 1500-MHz local-oscillator signal, and an I2C interface for parameter adjustment. The front end exhibits a gain of 83 dB, a noise figure of 2.8 dB, and an input-referred 1-dB compression point of -73.5 dBm preventing the front end from saturation while jammed. A path-to-path isolation of at least 30 dB leads to a high spatial resolution. The power consumption is 231.7 mW and 255.7 mW with and without interferers, respectively.