Erich Thallner

High-Performance Temporary Adhesives for Wafer Bonding Applications

Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without

Si/GaAs heterostructures fabricated by direct wafer bonding

Si/GaAs heterostructures were obtained by a low temperature direct wafer bonding (DWB) method which uses spin-on glass (SOG) intermediate layers. The use of intermediate SOG layers allows the fabrication of Si/GaAs heterostructures at processing temperatures lower than 200°C. The achieved bonding energy permits thinning down to a few microns of Si and GaAs wafers, respectively, using grinding procedures followed by chemical mechanical polishing (CMP). After thinning, the heterostructures sustained annealing temperatures of 450°C without damaging of the bonded interface. The above bonding procedure was successfully applied for bonding GaAs wafers to Si wafers with structured surfaces. A technology was developed based on this bonding method for producing universal GaAs-on-Si or Si-on-GaAs substrates.

Heterogeneous substrates for high-temperature and optical applications

Further applications of MEMS require the combination of different materials in order to combine different functions in one and the same system. Besides conventional techniques (layer deposition methods) semiconductor wafer direct bonding is expected to be an effective method to produce heterogeneous materials. Different examples for optical and high-temperature applications are presented (Si-based heterostructures, Si/GaAs heterostructures).