Markus Wimplinger

High-Performance Temporary Adhesives for Wafer Bonding Applications

Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without

Monolithic Two-Terminal III–V//Si Triple-Junction Solar Cells With 30.2% Efficiency Under 1-Sun AM1.5g

Stacking III-V p-n junctions on top of wafer-based silicon solar cells is a promising way to go beyond the silicon single-junction efficiency limit. In this study, triple-junction GaInP/AlxGa1-xAs//Si solar cells were fabricated using surface-activated direct wafer bonding. Metal-organic-vapor-phase-epitaxy-grown GaInP/AlxGa1-xAs top cells are bonded at low temperature to independently prepared wafer-based silicon cells. n-Si//n-GaAs interfaces were investigated and achieved bulk-like bond strength, high transparency, and conductivity homogeneously over 4-inch wafer area. We used transfer-matrix optical modeling to identify the best design options to reach current-matched two-terminal devices with different mid-cell bandgaps (1.42, 1.47, and 1.52 eV). Solar cells were fabricated accordingly and calibrated under AM1.5g 1-sun conditions. An improved Si back-side passivation process is presented, leading to a current density of 12.4 mA/cm2 (AM1.5g), measured for a flat Si cell below GaAs. The best 4 cm2 GaInP/GaAs//Si triple-junction cell reaches 30.2% 1-sun efficiency.

Thin wafer processing and chip stacking for 3D integration

The advantages as well as the technical feasibility of through silicon vias (TSV) and 3D integration have been widely acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps.

CMOS image sensor wafer-level packaging

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

Metal Thermocompression Wafer Bonding for 3D Integration and MEMS Applications

Due to the diffusion mechanism one of the most important aspects for the bonding process is to control the surface status. Contamination or native oxides may impact consistently on the process result (defect-free, high bond strength and particularly for 3D applications low resistivity). Metal oxides have different behavior and have to be treated accordingly. For example in case of Copper two different approaches are used in order to minimize the oxide-induced issues: metal surface protection with an organic layer (e.g. Benzotriazole) and oxide removal by wet etching or by heated gas treatment (e.g. forming gas). If this method works in case of Copper it doesn’t make it a general rule: in case of Aluminum, the native oxide is chemically very stable and can not be removed as in case of Copper. In such case other methods are employed (e.g. mechanical breakage of oxide).

Advanced wafer bonding solutions for TSV integration with thin wafers

Due mainly to the thermal budget of CMOS devices, bonding techniques compatible with CMOS processing are limited to direct oxide bonding, metal bonding, adhesive bonding, and various hybrids of those methods. In order to facilitate thin wafer processing with existing fab equipment, we developed total solutions for temporary bonding and debonding of carrier wafers. When it comes to TSV integration, the temporary bonding process based on a spin-on adhesive is becoming the industry standard over that with a lamination tape due to better edge protection, compatibility with topographic surfaces, and better stability at higher process temperatures. The benefits with a newly developed spin-on process include temperature stability over 250°C, compatibility with bumped surfaces, short debonding time, easy thermal release, slide-off debonding, and easy cleanup with polar solvents. It is being proven that our temporary bonding and debonding techniques offer time and cost efficiency for TSV integration processes utilizing existing and established equipment and technologies.

Soft UV-based nanoimprint lithography for large-area imprinting applications

The International Technology Roadmap for Semiconductors (ITRS) lays out a quite challenging path for the further development of the patterning techniques needed to create the ever-smaller feature sizes. In recent years the standard lithography reached its limits due to the diffraction effects encountered and the necessary complexity of compatible masks and projection optics. The restrictions on wavelength, in combination with high process and equipment costs, make low cost, simple imprinting techniques competitive with next generation lithography methods. Nanoimprint Lithography (NIL) is predicted as one candidate for the 32 nm and 22 nm technological nodes according to the ITRS. There are several NIL techniques which can be categorized depending on the process parameters and the imprinting method - either step & repeat or full wafer imprinting. A variety of potential applications has been demonstrated by using Nanoimprint Lithography (e.g. SAW devices, vias and contact layers with dual damascene imprinting process, bragg structures, patterned media) [1,2]. In Soft UV-NIL processes the overlay alignment accuracy was not demonstrated to be prepared for nanoelectronic devices; however other applications are already in high volume manufacturing such as the production of optical components (e.g. micro lenses).

3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Todays focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands. Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers. Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer. In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.

Thin wafer processing - yield enhancement through integrated metrology

Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM).

Recent progress in thin wafer processing

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D IC. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. While the majority of the device manufacturing steps on the front side of the wafer will be completed with the wafer still at full thickness, it will be temporarily mounted onto a carrier before thinning and processing of the features on its backside. Once the wafer reaches the temporary bonding step, it already represents a significant value, as it has already gone through numerous processing steps. For this reason, inspection of wafers prior to non-reworkable process steps is of great interest. Within the context of Temporary Bonding this consideration calls for inline metrology that allows for detection of excursions of the temporary bonding process in terms of adhesive thickness, thickness uniformity as well as bonding voids prior to thinning of the product wafer. This paper introduces a novel metrology solution capable of detecting all quality relevant parameters of temporarily bonded stacks in a single measurement cycle using an Infrared (IR) based measurement principle. Thanks to the IR based measurement principle, the metrology solution is compatible with both silicon and glass carriers. The system design has been developed with the inline metrology task in mind. This has led to a unique system design concept that enables scanning of wafers at a throughput rate sufficient to enable 100% inspection of all bonded wafers inline in the Temporary Bonding system. Both, current generation temporary bonding system throughputs and future high volume production system throughputs as required by the industry for cost effective manufacturing of 3D stacked devices were taken into account as basic specifications for the newly developed metrology solution. Sophisticated software algorithms allow for making pass/ fail decisions for the bonded stacks and triggering further inspection, processing and / or rework. Actual metrology results achieved with this novel system will be presented and discussed. In terms of adhesive total thickness variation (TTV) of bonded wafers, currently achieved performance values for postbond TTV will be reviewed in light of roadmaps as required by high volume production customers.