Ernst Kratschmer

Electron beam technology-SEM to microcolumn

As a continued effort to improve the performance of low energy scanning electron probe systems for application in microscopy, lithography, metrology, etc., miniaturized electron beam columns, approximately 3 mm in length, demonstrating a probe size of 10 nm with a beam current of >=1 nA at 1 keV, have been successfully developed. This paper presents current status, future directions and potential applications of these microcolumns.

Energy distributions of Zr/O/W Schottky electron emission

The energy distributions of electron emission from a Schottky emitter have been studied at tip temperatures from 1450 to 1800 K and angular current densities from 0.1 to 240 μA/sr. We have observed broadening of the energy distribution, with increase of angular current density and decrease of tip temperature, from 0.4 to 1.32 eV resulting from electron tunneling and electron–electron interaction. Good agreement between the experimental results and predictions from Monte Carlo simulation of the emission process is observed.

Graphene technology with inverted-T gate and RF passives on 200 mm platform

Wafer-scale graphene devices processed entirely in a standard 200 mm silicon fab are demonstrated for the first time. New embedded gate structures enable full saturation of the drain current in graphene FETs with sub-μm channels, resulting in high intrinsic voltage gain. In addition, passive devices were monolithically integrated with graphene transistors to form the first GHz-range graphene IC using large-scale CVD graphene. The demonstration of high performance graphene FETs and IC fabricated using a 200 mm platform is a major step in transitioning this promising material from a scientific curiosity into a real technology.

Electron-beam microcolumn technology and applications

A fully functional electron beam microcolumn, 3.5 mm in length, demonstrating a probe size of 10 nm and beam current >= 1 nA at 1 keV has been successfully developed. This paper presents its current status and future directions. Potential applications ranging from low cost scanning electron microscopy to arrays of such microcolumns for lithography, metrology, testing etc. will be discussed.

Imaging capabilities of proximity X-ray lithography at 70 nm ground rules

This paper discusses the resolution capabilities of proximity x-ray lithography (PXRL) system. Exposure characteristics of features designed at 150 nm pitch size: 75 nm dense lines with 1:1 duty ratio, 2D features at 1:1 and 1:2 duty ratios and isolated lines have been studied. Aerial image simulations were compared to the experimental data. Verification of the aerial image model has been accomplished by measurements of exposure windows of 100 nm and 125 nm nested lines. The PXRL aerial image parameter, equivalent penumbra blur, has been determined from the experimental data. Contributions from the synchrotron radiation x-ray source, stepper and the chemically amplified resist to the degradation of the aerial image have been evaluated. Patterning capability of PXRL at 75 nm feature size is compared to projection optics using the optical k1 factor as a common figure of merit. To facilitate the comparison, optical imagin was at pattern sizes currently manufacturable by the mainstream optical tools while the PXRL imaging was at 75 nm pattern size. Requirements for a PXRL system of manufacturing VLSI at 70 nm minimum feature sizes with the critical dimension control better than 10 percent are also discussed.

Trigate 6T SRAM scaling to 0.06 µm 2

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

Patterning of CMOS device structures for 40-80nm pitches and beyond

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.

200 mm wafer-scale integration of sub-20 nm sacrificial nanofluidic channels for manipulating and imaging single DNA molecules

We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged by fluorescence microscopy. Our method offers a manufacturable wafer-scale approach for CMOS-compatible bio-chip platform.

Electron beam lithography of sub-0.1μm circuits

Abstract This paper describes the high resolution electron beam system and the lithography processes developed for the fabrication of ultra high speed, sub-0.1μm silicon FET circuits and other projects where complex multi-level structures with highly accurate overlay are required. Noise sources and short term instability in the lithography tool have been reduced to less than 4nm peak-to-peak, while still accepting 125mm wafers. Devices and circuits have been fabricated with 70nm polysilicon gates and level-to-level overlay of typically 30nm over a 250μm field. The devices have yielded record transconductance results of more than 910mS/mm at 77 K, and have shown clear evidence of velocity overshoot. Device switching speeds of 13 picoseconds have been observed in ring oscillator circuits.

Experimental realization of deep-subwavelength confinement in dielectric optical resonators

Dielectric cavities support record low mode volumes by incorporating subwavelength features into photonic crystal unit cells. The ability to highly localize light with strong electric field enhancement is critical for enabling higher-efficiency solar cells, light sources, and modulators. While deep-subwavelength modes can be realized with plasmonic resonators, large losses in these metal structures preclude most practical applications. We developed an alternative approach to achieving subwavelength localization of the electric and displacement fields that is not accompanied by inhibitive losses. We experimentally demonstrate a dielectric bowtie photonic crystal structure that supports mode volumes commensurate with plasmonic elements and quality factors that reveal ultralow losses. Our approach opens the door to the extremely strong light-matter interaction regime with, simultaneously incorporating both an ultralow mode volume and an ultrahigh quality factor, that had remained elusive in optical resonators.