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Dive into the research topics where Etsuro Sugimata is active.

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Featured researches published by Etsuro Sugimata.


IEEE Transactions on Nanotechnology | 2006

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

Yongxun Liu; Shinya Kijima; Etsuro Sugimata; Meishoku Masahara; Kazuhiko Endo; Takashi Matsukawa; Kenichi Ishii; Kunihiro Sakamoto; Toshihiro Sekigawa; Hiromi Yamauchi; Yoshifumi Takanashi; Eiichi Suzuki

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phi<sub>TiN</sub>) slightly decreases with increasing nitrogen (N<sub>2</sub>) gas flow ratio, R<sub>N</sub>=N<sub>2</sub>/(Ar+N<sub>2</sub>) in the sputtering, from 17% to 100%. The experimental threshold voltage (V<sub>th</sub>) dependence on the R<sub>N</sub> shows that the more R<sub>N</sub> offers the lower V<sub>th</sub> for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different R<sub>N</sub> showed that the more amount of nitrogen is introduced into the TiN films with increasing R<sub>N</sub>, which suggests that the lowering of phi <sub>TiN</sub> with increasing R<sub>N</sub> should be related to the increase in nitrogen concentration in the TiN film. The desirable V<sub>th</sub> shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n<sup>+</sup> poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication


IEEE Transactions on Electron Devices | 2006

Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

Kazuhiko Endo; Shuichi Noda; Meishoku Masahara; T. Kubota; Takuya Ozaki; Seiji Samukawa; Yongxun Liu; Kenichi Ishii; Yuki Ishikawa; Etsuro Sugimata; Takashi Matsukawa; Hidenori Takashima; Hiromi Yamauchi; Eiichi Suzuki

A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up and photon-radiation damages caused by the plasma. The fabricated FinFETs realize a higher device performance (i.e., higher electron mobility) than that obtained by using a conventional reactive-ion etching. The improved mobility is well explained by the NB-etched atomically flat surface. These results strongly support the effectiveness of the NB technology for nanoscale CMOS fabrication


IEEE Transactions on Nanotechnology | 2007

Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation

Kazuhiko Endo; Yuki Ishikawa; Yongxun Liu; Kenichi Ishii; Takashi Matsukawa; Shin-ichi O'uchi; Meishoku Masahara; Etsuro Sugimata; Jyunichi Tsukada; Hiromi Yamauchi; Eiichi Suzuki

A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode


Japanese Journal of Applied Physics | 2006

Experimental Study of Effective Carrier Mobility of Multi-Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111) Channel Surface Fabricated by Orientation-Dependent Wet Etching

Yongxun Liu; Etsuro Sugimata; Kenichi Ishii; Meishoku Masahara; Kazuhiko Endo; Takashi Matsukawa; Hiromi Yamauchi; Shin-ichi O'uchi; Eiichi Suzuki

We present an experimental study of effective carrier mobility ( µeff) of multi-fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs) with a (111) channel surface fabricated by orientation-dependent wet etching. The peak values of the obtained µeff of electrons and holes are approximately 300 and 160 cm2/(V s), respectively, which are close to those in (111) bulk metal–oxide–semiconductor field-effect transistors (MOSFETs). Moreover, the effective electric field (Eeff) dependence of the µeff of electrons and holes shows a good agreement with the mobility universal curves of (111) bulk MOSFETs. These results indicate that the quality and channel surface roughness of Si-fins by orientation-dependent wet etching are excellent. The obtained results of µeff are very useful for the modeling and design of FinFET-complementary metal–oxide–semiconductor (CMOS) circuits and the developed wet etching technique is very attractive in the fabrication of ultrathin and high-quality Si-fin channels.


international electron devices meeting | 2005

Damage-free neutral beam etching technology for high mobility FinFETs

Kazuhiko Endo; Shuichi Noda; Meishoku Masahara; T. Kubota; Takuya Ozaki; Seiji Samukawa; Yongxun Liu; Kenichi Ishii; Yuki Ishikawa; Etsuro Sugimata; Takashi Matsukawa; Hidenori Takashima; Hiromi Yamauchi; Eiichi Suzuki

Our newly developed neutral beam (NB) etching accomplished the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-fins for the first time. The fabricated FinFETs realized higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the NB etched atomically-flat surface. Our new results strongly support the effectiveness of the NB technology for the nano-scale CMOS fabrication


Japanese Journal of Applied Physics | 2006

Fabrication of a Vertical-Channel Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Using a Neutral Beam Etching

Kazuhiko Endo; Shuichi Noda; Meishoku Masahara; T. Kubota; Takuya Ozaki; Seiji Samukawa; Yongxun Liu; Kenichi Ishii; Yuki Ishikawa; Etsuro Sugimata; Takashi Matsukawa; Hidenori Takashima; Hiromi Yamauchi; Eiichi Suzuki

A vertical ultrathin-channel (UTC) formation process using a low-energy neutral beam etching (NBE) for a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed for the first time. The NBE can perfectly eliminate the charge build-up and photon radiation damages from the plasma. By utilizing the NBE, fin-type vertical MOSFETs with damage-less smooth sidewalls were successfully fabricated. The fabricated FinFETs realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically-flat surface utilizing by the NBE.


Japanese Journal of Applied Physics | 2006

Demonstration and Analysis of Accumulation-Mode Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor

Meishoku Masahara; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Shin-ichi O'uchi; Kenichi Ishii; Etsuro Sugimata; Eiichi Suzuki

The property of an accumulation-mode double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) has thoroughly been investigated on the basis of experimental data and simulation results. Both accumulation- and inversion-mode DG-MOSFETs have been fabricated by novel vertical DG-MOSFET fabrication process technology. It is experimentally demonstrated that accumulation-mode DG-MOSFETs show a severe influence of channel thickness (TSi) on threshold voltage (Vth) and subthreshold slope (S) as compared with inversion-mode ones. By decreasing TSi, however, S is dramatically improved to the same value as that for the inversion-mode one. The short-channel effects (SCEs) for the accumulation-mode DG-MOSFETs have been explored using device simulation. The simulation result shows that, by decreasing TSi to 10 nm, the trend of the SCEs for the accumulation-mode DG-MOSFETs becomes the same as that for the inversion-mode one down to an effective gate length of 10 nm. It is also demonstrated that, by using n+-DGs, an appropriate Vth as well as a low S can be attained for an accumulation-mode PMOS vertical DG-MOSFET.


Applied Physics Letters | 2006

Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

Meishoku Masahara; Yongxun Liu; Kazuhiko Endo; Takashi Matsukawa; Kunihiro Sakamoto; Kenichi Ishii; Shin-ichi O’uchi; Etsuro Sugimata; Hiromi Yamauchi; Eiichi Suzuki

A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8mV/decade was achieved with a channel thickness of 20nm.


Japanese Journal of Applied Physics | 2006

New Fabrication Technology of Fin Field Effect Transistors Using Neutral-Beam Etching

Kazuhiko Endo; Shuichi Noda; Takuya Ozaki; Seiji Samukawa; Meishoku Masahara; Yongxun Liu; Kenichi Ishii; Hidenori Takashima; Etsuro Sugimata; Takashi Matsukawa; Hiromi Yamauchi; Yuki Ishikawa; Eiichi Suzuki

Ultrathin-channel formation of a vertical-type double-gate metal oxide semiconductor field effect transistor using a low-energy neutral-beam etching (NBE) is proposed. The NBE can completely eliminate charge buildup and photon radiation damage from the plasma. By optimizing NBE conditions, rectangular vertical channels were fabricated with a SiO2 hard mask under low-energy NBE conditions.


Physica C-superconductivity and Its Applications | 2002

Flux-flow cavity resonance modes in intrinsic Josephson junctions by Bi2Sr2CaCu2Ox thin films

H. Fujino; Hirotake Yamamori; Etsuro Sugimata; K. Matsumoto; Shigeki Sakai

Abstract A 3-μm long intrinsic Josephson junction has been fabricated using a Bi 2 Sr 2 CaCu 2 O x thin film. Current vs voltage measurement shows characteristics of a fivefold stacked Josephson junction. In the magnetic field (1–2 T) parallel to the junction planes, the current vs voltage curves at the low voltage region exhibit fine sub-branch structures. Numerical simulation results show fine structures as well, which are due to the flux-flow cavity resonance, and support that the in-phase motion may occur in the present experimental conditions.

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Eiichi Suzuki

Tokyo Institute of Technology

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Kazuhiko Endo

National Institute of Advanced Industrial Science and Technology

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Kenichi Ishii

National Institute of Advanced Industrial Science and Technology

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Takashi Matsukawa

National Institute of Advanced Industrial Science and Technology

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Hiromi Yamauchi

National Institute of Advanced Industrial Science and Technology

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Meishoku Masahara

National Institute of Advanced Industrial Science and Technology

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Yongxun Liu

National Institute of Advanced Industrial Science and Technology

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Hidenori Takashima

National Institute of Advanced Industrial Science and Technology

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Shigeki Sakai

National Institute of Advanced Industrial Science and Technology

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Yuki Ishikawa

National Institute of Advanced Industrial Science and Technology

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