Hidenori Takashima

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

The FT-FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel have successfully been fabricated by using newly developed orientation-dependent wet etching. The flexible V/sub th/ controllability by using one of the double gates as a control gate and by the synchronized driving mode operation is experimentally confirmed. The developed processes are attractive for the fabrication of the advanced separate-gates FinFET for a flexible function VLSI circuit.

Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up and photon-radiation damages caused by the plasma. The fabricated FinFETs realize a higher device performance (i.e., higher electron mobility) than that obtained by using a conventional reactive-ion etching. The improved mobility is well explained by the NB-etched atomically flat surface. These results strongly support the effectiveness of the NB technology for nanoscale CMOS fabrication

Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors

The dependence of short-channel effects (SCEs) on the cross-sectional channel shape of the fin-type double-gate metal oxide semiconductor field-effect transistors (MOSFETs) has been experimentally investigated from the viewpoint of fin fabrication. The three types of fin-type double-gate MOSFETs (FinFETs) with a rectangular-cross-section channel on a (110)-oriented silicon-on-insulator (SOI) wafer, and a triangular and trapezoidal channels on a (100)-oriented SOI wafer were fabricated using the same orientation-dependent wet etching process. The experimental results show that the SCEs in rectangular-cross-section silicon (Si)-fin channel devices are well suppressed compared with those in a triangular or a trapezoidal Si-fin channel device fabricated using a similar mask pattern, in the regimes of the gate length of less than 85 nm and Si fin height of larger than 65 nm. The presented experimental results are valuable for FinFET design and fabrication.

Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography

We present the Fin-type double-gate metal-oxide-semiconductor field-effect transistors (FXMOSFETs, the XMOS transistor was named because its cross section resembles the Greek letter Ξ which corresponds to the English letter X) with ideal rectangular fin cross section, for the first time, using (110)-oriented silicon-on-insulator (SOI) wafers. The nanoscale silicon (Si)-Fin has successfully been fabricated by orientation-dependent etching using an etchant of 2.38% tetramethylammonium hydroxide (TMAH) solution. The almost ideal subthreshold slope of 64 mV/decade was obtained for the fabricated 20 nanometers (nm) Si-Fin and 145 nm gate length FXMOSFET. This excellent subthreshold characteristic experimentally shows that the interface property of the Si-Fin channel with (111)-oriented sidewalls is suitable to realize a high-performance FXMOSFET. The electrical characteristics of the fabricated FXMOSFETs in the 20–100 nm Si-Fin width regime have been systematically investigated. The experimental results indicate that the short-channel effects (SCEs) can be effectively suppressed by reducing the Si-Fin width to 20 nm or less. The developed processes are promising for fabrication of the FXMOSFET as a future nano-silicon device.

Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

The electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs (FXMOSFETs) fabricated by a wet process have experimentally and systematically been investigated. The almost ideal S-slope of 64 mV/decade was obtained for the fabricated 20 nm Si-Fin and 125 nm gate-length FXMOSFET. This excellent subthreshold characteristic shows that the quality of the rectangular Si-Fin channel with (111)-oriented sidewall is good enough to realize high-performance FXMOSFETs. The current and transconductance multiplication accurately proportional to a number of 30 nm Si-Fin channels was confirmed in the fabricated multi-fin FXMOSFETs. The systematic investigation of the electrical characteristics of the fabricated FXMOSFETs in the 20-110-nm Si-Fin and 2.3-5.2-nm gate oxide regimes reveals that short-channel effects can be effectively suppressed by reducing the Si-Fin thickness to 20 nm or less. The developed processes are quite attractive for fabrication of ultranarrow Si-Fin channel double-gate MOSFETs.

Damage-free neutral beam etching technology for high mobility FinFETs

Our newly developed neutral beam (NB) etching accomplished the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-fins for the first time. The fabricated FinFETs realized higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the NB etched atomically-flat surface. Our new results strongly support the effectiveness of the NB technology for the nano-scale CMOS fabrication

Investigation of N-Channel Triple-Gate Metal?Oxide?Semiconductor Field-Effect Transistors on (100) Silicon On Insulator Substrate

We have investigated the fabrication processes and device characteristics for n-channel triple-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100) silicon-on-insulator substrates. By optimizing the diagonal ion implantation conditions for the narrow fin channel, the fabricated triple-gate device showed an electron mobility almost compatible to a planar MOSFET with a supreme subthreshold slope of 64 mV/decade and drain induced barrier lowering (DIBL) of 15 mV/V.

Fabrication of a Vertical-Channel Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Using a Neutral Beam Etching

A vertical ultrathin-channel (UTC) formation process using a low-energy neutral beam etching (NBE) for a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed for the first time. The NBE can perfectly eliminate the charge build-up and photon radiation damages from the plasma. By utilizing the NBE, fin-type vertical MOSFETs with damage-less smooth sidewalls were successfully fabricated. The fabricated FinFETs realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically-flat surface utilizing by the NBE.

New Fabrication Technology of Fin Field Effect Transistors Using Neutral-Beam Etching

Ultrathin-channel formation of a vertical-type double-gate metal oxide semiconductor field effect transistor using a low-energy neutral-beam etching (NBE) is proposed. The NBE can completely eliminate charge buildup and photon radiation damage from the plasma. By optimizing NBE conditions, rectangular vertical channels were fabricated with a SiO2 hard mask under low-energy NBE conditions.