Rodrigo Picos

Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures

In this paper, a low-cost method to verify functional specifications of analog VLSI circuits is proposed. The method is based on the analysis of Lissajous signatures combined with regression techniques. In order to obtain Lissajous signatures, the observation space is partitioned into zones using hyperplanes, and a set of integer values used as the digital signature of the circuit is generated by Lissajous curve zone crossings. A predictor function obtained by nonlinear regression techniques predicts the functional specification parameters of the circuit under consideration. The viability of this methodology is analyzed and applied to verify the center frequency f 0 of a bandpass biquad filter. Experimental measurements show an accurate prediction of the center frequency of the designed filter.

Floating Gate CMOS Dosimeter With Frequency Output

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

Application of Predictive Oscillation-Based Test to a CMOS OpAmp

A predictive oscillation-based test (POBT) strategy, combined with supply current monitoring, is proposed as an alternative to the specification-based test of analog circuits. According to our simulation results, the combination of both techniques is excellent in predicting the main performance parameters of a CMOS operational amplifier (OpAmp) (dc gain, bandwidth, and slew rate) from test observables such as oscillation frequency and variations on the supply current. Considering tolerances in the fabrication process, a set of mapping functions has been found by circuit simulation, giving correlation coefficients higher than 0.999 and RMS prediction errors below 1.5%. A set of 19 fabricated circuits has been measured in both normal and test modes. The correlation between performance parameters and test observables, which are both measured, gives RMS errors of 0.65% for the dc gain, 11.30% for the bandwidth, and 4.12% for the slew rate.

A BICS for CMOS OpAmps by Monitoring the Supply Current Peak

We present a Built-In-Current-Sensor (BICS) based on monitoring a signature of the supply current peak of CMOS OpAmps using the oscillation-test-strategy. The BICS takes a weighted sample of the current through two OpAmp current branches and monitors a signature of the peak value under oscillation. Two current-based comparators and some digital circuitry are used to provide a pass/fail flag. Simulation results demonstrate a high defect coverage with a very small impact both on the OpAmp nominal operation and the area overhead.

Predictive test strategy for CMOS RF mixers

In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local oscillator (LO) signal as the only test stimuli. The second strategy uses additional test circuitry, a generator, and an auxiliary mixer. Prediction accuracies are similar in both strategies, but the test observables in the second one are easier to be obtained.

Alternate characterization technique for static random-access memory static noise margin determination

The cell static noise margin (SNM) is widely used as a stability criterion for static random-access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable. In this work, we present a methodology that provides an indirect measurement of the SNM on a per-cell basis for six-transistor SRAMs. It is based on combining an Adaptive Neuro-Fuzzy Inference System (ANFIS) with circuit-level cell experimentally measurable parameters as input variables to the tool. We show that it is possible to obtain the SNM for individual memory cells using the same experimental setup and data than that required for shmoo plot measurements. Results confirm that the SNM can be experimentally estimated with a relative error compared with electrical simulations that is below 0.5%. Copyright

Experimental results on BIC sensors for transient current testing

In this work experimental results on a built-in current sensor for dynamic current testing, i(t), based on integration concepts are presented. The experimental validation proposed in this work is done through a VLSI CMOS circuit implemented in a 0.7 μm technology. Different experiences have been developed analyzing the detectability of several kind of defects through this technique. The encouraging results obtained present this technique as an attractive complement to boolean and I testing.

Directed Genetic algorithms for OTFT model parameter extraction

An improvement on the parameter extraction technique for compact device models based on Genetic algorithms is presented. The use of fuzzy logic based rules to direct the evolution of the genetic algorithm enhances the convergence and the physical meaning of the parameters is preserved. Another advantage of this method is that the fuzzy rules can be applied just to a reduced set of model parameters. The parameter extraction procedure is applied to find the parameters in an OTFT model from a set of experimental data. Agreement between measured and modeled DC I-V characteristics is excellent. Moreover, the parameter values obtained with this procedure agree remarkably with the ones obtained by a direct extraction method.

A Module for BiST of CMOS RF Receivers

A module to perform a built-in self-test in CMOS RF receivers is presented. The module is associated with a test strategy consisting of measuring the main performance parameters of the single building blocks individually. Circuitry overhead, however, is kept low by using some blocks as part of the test set-up and reusing them. The test overhead has also been reduced by replacing direct determination of performance parameters with their estimation. The test methodology has been applied to a mixer in the first down conversion stage of a GSM receiver, estimating its conversion gain, 1dB compression and third-order interception points. Using the output of the IF amplifier as the only testing point, the rms errors in the estimation of the above mentioned parameters are 1.5, 3.0 and 2.7%, respectively.

Predictive Oscillation Based Test of CMOS circuits

Two different CMOS circuits has been used to check the predictive oscillation based test (POBT) approach, combined with supply current monitoring technique. These circuits are a two stage op amp and a biquad filter composed by two transconductance amplifiers (OTA). The combination of both techniques has given excellent results in predicting the main performance parameters of the circuits as DC gain, bandwidth or slew-rate in the opamp and cut-off frequency, quality factor or rise time in the filter. When considering tolerances in the fabrication process, correlation coefficients higher than 0.998 for the opamp and 0.95 for the biquad filter have been found. These good results open the door to a new built in test strategy, and alleviates the need of more complex techniques to enhance the efficiency of the POBT requiring sophisticated acquisition systems