Eun Sik Jung

A Study on Characteristic Improvement of IGBT with P-floating Layer

A power semiconductor device, usually used as a switch or rectifier, is very significant in the modern power industry. The power semiconductor, in terms of its physical properties, requires a high breakdown voltage to turn off, a low on-state resistance to reduce static loss, and a fast switching speed to reduce dynamic loss. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. Although the low doping concentration in the drift region increases the breakdown voltage, the on-state resistance that is increased along with it makes the static loss characteristic deteriorate. On the other hand, although the high doping concentration in the drift region reduces on-state resistance, the breakdown voltage is decreased, which limits the scope of its applications. This addresses the fact that breakdown voltage and on-state resistance are in a trade-off relationship with a parameter of the doping concentration in the drift region. Such a trade-off relationship is a hindrance to the development of power semiconductor devices that have idealistic characteristics. In this study, a novel structure is proposed for the Insulated Gate Bipolar Transistor (IGBT) device that uses conductivity modulation, which makes it possible to increase the breakdown voltage without changing the on-state resistance through use of a P-floating layer. More specifically in the proposed IGBT structure, a P-floating layer was inserted into the drift region, which results in an alleviation of the trade-off relationship between the on-state resistance and the breakdown voltage. The increase of breakdown voltage in the proposed IGBT structure has been analyzed both theoretically and through simulations, and it is verified through measurement of actual samples.

A Study on the Design and Electrical Characteristics Enhancement of the Floating Island IGBT with Low On-Resistance

Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.

Design of Current-Type Readout Integrated Circuit for 160 × 120 Pixel Array Applications

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 ㎷/℃, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 ㎛ standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance [1]. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don’t have a great effect on temperature change.

Design and Fabrication of Super Junction MOSFET Based on Trench Filling and Bottom Implantation Process

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

Investigation of the layout and optical proximity correction effects to control the trench etching process on 4H-SiC

Although trench gate and super-junction technology have micro-trench problems when applied to the SiC process due to the material characteristics. In this paper, area effects are analyzed from the test element group with various patterns and optical proximity correction (OPC) methods are proposed and analyzed to reduce micro-trenches in the SiC trench etching process. First, the loading effects were analyzed from pattern samples with various trench widths (Wt). From experiments, the area must limited under a proper size for a uniform etching profile and reduced micro-trenches because a wider area accelerates the etch rate. Second, the area effects were more severely unbalanced at corner patterns because the corner pattern necessarily has an in-corner and out-corner that have different etching areas to each other. We can balance areas using OPC patterns to overcome this. Experiments with OPC represented improved micro-trench profile from when comparing differences of trench depth (Δdt) at out corner and in corner. As a result, the area effects can be used to improve the trench profile with optimized etching process conditions. Therefore, the trench gate and super-junction pillar of the SiC power MOSFET can have an improved uniform profile without micro-trenches using proper design and OPC.

Study of 4H-SiC Junction Barrier Schottky(JBS) Diode Using Various Junction Structures

In this paper, to verify implant effect characteristics variation by stripe type, grid type and circle type, the P+ implant patterning was studied. The result of two-dimensional simulation was controlled by adjusting the relative area of Schottky and p–n junction dimensions of the device, which is easily implemented during the device layout design. 4H-SiC JBSs with three types have been successfully fabricated and breakdown voltage in the range of 1694–2051 V has been achieved. The results of fabricated JBSs, show that the stripe type JBSs combine the best features of the P+ implant patterns.

An Analog Front-End IC Design for 320

We propose an analog front-end integrated circuit (IC) design for a readout IC (ROIC), which applies a fixed- voltage-bias sensing method with a capacitance transimpedance amplifier (CTIA) to an input stage in order to simplify the circuit structure of the ROIC and the IR sensor characteristic control. For a sample-and-hold stage, in order to display and control a signal detected by the IR sensor using a 2-D focal plane array, a differential delta sampling circuit is proposed, which effectively removes the fixed pattern noise. In addition, a two-stage variable-gain amplifier equipped with a rail-to-rail fully differential operational amplifier is applied to the ROIC to achieve high voltage sensitivity. The output characteristic of the proposed device is 30.84 mV/K and the linearity error rate is less than 0.07%. After checking the performance of the ROIC using an HSPICE simulation, the chip is manufactured and measured using the United Microelectronics Corporation Japan 0.35-μm standard CMOS process to confirm that the simulation results from the actual design are in close agreement with the measurement results.

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Power semiconductor devices have been the major backbone for high-power electronic devices. One of important parameters in view of power semiconductor devices often characterize with a high breakdown voltage. Therefore, many efforts have been made, since the development of the Insulated Gate Bipolar Transistor (IGBT), toward having higher level of breakdown voltage, whereby the typical design thereof is focused on the structure using the field ring. In this study, in an attempt to make up more optimized field-ring structure, the characteristics of the field ring were investigated with the use of theoretical arithmetic model and methodologically the design of experiments (DOE). In addition, the IGBT having the field-ring structure was designed via simulation based on the finding from the above, the result of which was also analyzed. Lastly, the current study described the trench field-ring structure taking advantages of trench-etching process having the improved field-ring structure, not as simple as the conventional one. As a result of the simulation, it was found that the improved trench field-ring structure leads to more desirable voltage divider than relying on the conventional field-ring structure.

240 Microbolometer Array Applications

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.