Man Young Sung

A FERROELECTRIC BASED PASSIVE RFID TAG FOR UHF (860–960 MHz) BAND

ABSTRACT For a longer working distance between passive tags and the reader, the ferroelectric based technologies are proposed in UHF (860–960 MHz) band transponder. The small ferroelectric capacitor layout area with a stacked capacitor structure over circuit region and a large dielectric permittivity of 250 to 500 and small 1T1C cell array layout area with simple 2T2C based reference scheme allow small chip size. The low operation voltage of 1.5 V to 2.0 V without high voltage boosting scheme also contribute to small power consumption and low cost.

Core Circuit Technologies for PN-Diode-Cell PRAM

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90㎚ technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

Dual Field Communication Scheme for UHF (860–960 MHz) Gen2 RFID Chip

The proposed UHF Gen2 RFID chip expands its applications to both FFC and NFC through dual field communication scheme with the dual antenna ports. An RF front end circuit with dual field communication antenna ports and the embedded FeRAM technology on the passive UHF Gen2 RFID chip enables the excellent operating performances and the low cost chip for the tag chip applications from the item level to pallet. The metal-ferroelectric-metal (MFM) capacitor, which is the replacement capacitor device for metal-insulator-metal (MIM) or poly-insulator-poly (PIP), is composed of the ferroelectric material as a dielectric insulator. The MFM capacitor is made simultaneously during the FeRAM memory cell process integration without any additional process integration cost. The MFM capacitor of PZT with the thickness of 0.15μm has the high capacitance value of 20–40 fF at unit μm2 area size. The MFM can be stacked over the CMOS layout area, which saves dramatically the capacitor layout area. The MFM capacitor also has the high breakdown voltage at the thickness of 0.15 μm, which enhances the reliability in the surging electrostatic discharge (ESD) current into the dual antenna ports. The pumping capacitors of the multi-stage voltage pump are composed of the multiple MFM capacitors of the capacitance value of the element device of 1–2 pF. The reservoir capacitors of the VDD power line also are composed of the MFM capacitors with the total capacitance value of 500–1000 pF. The rectification diode device is composed of the near zero threshold voltage NMOS (ZNMOS) transistor with a threshold voltage level of 0.1–0.2 V.

FLOATING-BASE BJT TYPE ESD DEVICE FOR RFID CHIP

ABSTRACT N-WELL floating base is sandwiched between P+ emitter and P-WELL collector in the proposed floating base vertical PNP electro-static discharge (ESD) protection device. Floating base bipolar junction transistor (BJT) ESD protection device increases the current performance of the parasitic BJT in the ESD mode. During the negative voltage phase of RF antenna signal, the negative voltage range of RF antenna signal is extended to around −10 V at the high RF power field without latch-up failure. The minimum P+ anode layout area of the floating base type BJT ESD device is 400 μm2 for the target ESD voltage of 2000 V in human body model (HBM) mode. The parasitic capacitance of the floating base type BJT ESD protection device is about 0.4 pF. The layout area of the proposed floating base type BJT ESD protection device is 50% smaller that of the conventional NMOS diode type ESD protection device for the target ESD voltage of 2000 V in HBM mode. The rewards of the floating base type BJT ESD device will come in the form of improved yields, higher reliability, and substantially lower costs of RFID chip manufacturing.

A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY

ABSTRACT This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data ‘1’ preserve or data ‘0’ write cycle after the first sub-write cycle of data ‘1’ write to all active cells. The data ‘1’ is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).

Bidirectional floating-base BJT ESD protected RFID chip

ABSTRACT The maximum peak-to-peak radio frequency (RF) signal antenna voltage level can be extended to reach to over 12 Vpp, −6 V to +6 V. Thus it is desirable that the electro-static discharge (ESD) device does not turn on at the normal operating RF antenna signal voltage level. The turn-on threshold negative voltage of the ESD device of the PN diode type is around −0.5 V in the conventional radio frequency identification (RFID) chip. The asymmetric threshold voltage characteristics of the ESD device of the RFID chip makes the distortion of the RF antenna signal at the high intensity RF input field. In the proposed floating base vertical PNP ESD device, N-type doped N-WELL floating base is sandwiched between two p-type P+ emitter and P-WELL collector. Floating base BJT ESD device enhances the performance of parasitic BJT current in the ESD mode. During the negative voltage phase of RF antenna input signal, the negative voltage of RF antenna input is extended to around −10 V. This extension of RF antenna input operation voltage range makes to prevent from any distortion of RF antenna signal at the high RF input field. The measured HBM ESD protection level of the floating base BJT ESD device is over 2000 V with the P+ anode layout area of 400 μm2.

A Nonvolatile Refresh Scheme Adopted 1T-FeRAM for Alternative 1T-DRAM

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

CRYPTO BASED EPC C1G2 UHF (860 MHz–960 MHz) PASSIVE RFID TAG CHIP

ABSTRACT The metal-ferroelectric-metal (MFM) capacitor in ferroelectric random access memory (FeRAM) security embedded RFID chip is used not only in the memory cell region but also used in the analog and digital circuit area for low cost capacitance device and high security algorithm. MFM based security FeRAM braces for a wide range of security threats such as reverse engineering, cloning, and tampering. High security performance solution of on-chip FeRAM based register key is implemented to prepare against security attacking. RF transferring sensitivity properties with MFM capacitor are almost same or better than that with poly-insulator-poly (PIP) capacitor and metal-insulator-metal (MIM), and MOS capacitor. The measured power consumption of FeRAM embedded RFID chip without crypto processor engine is about 10μ W with the write sensitivity of -18dBm.

A Graded Sense-Load Scheme and Cell Data Distribution in FeRAM

The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub_block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μ C/cm2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μ C/cm2.