Eunha Lee

Amorphous hafnium-indium-zinc oxide semiconductor thin film transistors

We developed amorphous hafnium-indium-zinc oxide (HIZO) thin films as oxide semiconductors and investigated the films electrically and physically. Adding of hafnium (Hf) element can suppress growing the columnar structure and drastically decrease the carrier concentration and hall mobility in HIZO films. The thin film transistors (TFTs) with amorphous HIZO active channel exhibit good electrical properties with field effect mobility of around 10 cm2/Vs, S of 0.23 V/decade, and high Ion/off ratio of over 108, enough to operate the next electronic devices. In particular, under bias-temperature stress test, the HIZO TFTs with 0.3 mol % (Hf content) showed only 0.46 V shift in threshold voltage, compared with 3.25 V shift in HIZO TFT (0.1 mol %). The Hf ions may play a key role to improve the instability of TFTs due to high oxygen bonding ability. Therefore, the amorphous HIZO semiconductor will be a prominent candidate as an operation device for large area electronic applications.

High-performance amorphous gallium indium zinc oxide thin-film transistors through N2O plasma passivation

Amorphous-gallium-indium-zinc-oxide (a-GIZO) thin filmtransistors (TFTs) are fabricated without annealing, using processes and equipment for conventional a-Si:H TFTs. It has been very difficult to obtain sound TFT characteristics, because the a-GIZO active layer becomes conductive after dry etching the Mo source/drain electrode and depositing the a-SiO2 passivation layer. To prevent such damages, N2O plasma is applied to the back surface of the a-GIZO channel layer before a-SiO2 deposition. N2O plasma-treated a-GIZO TFTs exhibit excellent electrical properties: a field effect mobility of 37cm2∕Vs, a threshold voltage of 0.1V, a subthreshold swing of 0.25V/decade, and an Ion∕off ratio of 7.

180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

In this article, we propose a novel hybrid complementary metal oxide semiconductor (CMOS) image sensor architecture utilizing nanometer scale amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFT) combined with a conventional Si photo diode. This approach will overcome the loss of quantum efficiency and image quality due to the downscaling of the photodiode. The 180nm gate length a-IGZO TFT exhibits remarkable short channel device performance including a low 1/ƒ noise and a high output gain, despite fabrication temperatures as low as 200°C. The excellent device performance has been achieved by a double layer gate dielectric (Al2O3/SiO2) and a trapezoidal active region formed by a tailored etching process. A self aligned top gate structure was employed for low parasitic capacitance. 3D process simulation tools were applied to optimize a four pixel CMOS image sensor structure. The results demonstrate how our stacked hybrid device approach contributes to new device strategies in image sensor architectures. We expect that this approach is applicable to numerous devices and systems in future micro- and nano-electronics.

Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors

We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/drain region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/drain region was divided into In-rich and In-deficient regions. The a-GIZO TFT also had a constant sheet resistance of 1 kΩ/◻ for a film thickness of over 40 nm. The interface between the source/drain Mo metal and the Ar plasma-treated a-GIZO indicated a good Ohmic contact and a contact resistivity of 50 μΩ cm2.

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm2/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.

Short Channel Characteristics of Gallium–Indium–Zinc–Oxide Thin Film Transistors for Three-Dimensional Stacking Memory

Amorphous gallium-indium-zinc-oxide (GIZO) thin film transistors with short channels of 50 nm were successfully fabricated by e-beam lithographic patterning. The GIZO thin film transistors showed a high mobility of 8.2 cm2/Vldrs with on-to-off current ratios up to 106. Excellent short channel characteristics were also obtained with a small shift of the threshold voltages and no degradation of subthreshold slopes as VDS increased, even with short channel lengths of less than 100 nm. These promising results indicate that the GIZO thin film transistors could be a candidate for selection transistors in 3-D cross point stacking memory.

Anion control as a strategy to achieve high-mobility and high-stability oxide thin-film transistors

Ultra-definition, large-area displays with three-dimensional visual effects represent megatrend in the current/future display industry. On the hardware level, such a “dream” display requires faster pixel switching and higher driving current, which in turn necessitate thin-film transistors (TFTs) with high mobility. Amorphous oxide semiconductors (AOS) such as In-Ga-Zn-O are poised to enable such TFTs, but the trade-off between device performance and stability under illumination critically limits their usability, which is related to the hampered electron-hole recombination caused by the oxygen vacancies. Here we have improved the illumination stability by substituting oxygen with nitrogen in ZnO, which may deactivate oxygen vacancies by raising valence bands above the defect levels. Indeed, the stability under illumination and electrical bias is superior to that of previous AOS-based TFTs. By achieving both mobility and stability, it is highly expected that the present ZnON TFTs will be extensively deployed in next-generation flat-panel displays.

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Source/Drain Formation of Self-Aligned Top-Gate Amorphous GaInZnO Thin-Film Transistors by

The source/drain region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/drain region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.

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A novel method to design metal oxide thin-film transistor (TFT) devices with high performance and high photostability for next-generation flat-panel displays is reported. Here, we developed bilayer metal oxide TFTs, where the front channel consists of indium-zinc-oxide (IZO) and the back channel material on top of it is hafnium-indium-zinc-oxide (HIZO). Density-of-states (DOS)-based modeling and device simulation were performed in order to determine the optimum thickness ratio within the IZO/HIZO stack that results in the best balance between device performance and stability. As a result, respective values of 5 and 40 nm for the IZO and HIZO layers were determined. The TFT devices that were fabricated accordingly exhibited mobility values up to 48 cm(2)/(V s), which is much elevated compared to pure HIZO TFTs (∼13 cm(2)/(V s)) but comparable to pure IZO TFTs (∼59 cm(2)/(V s)). Also, the stability of the bilayer device (-1.18 V) was significantly enhanced compared to the pure IZO device (-9.08 V). Our methodology based on the subgap DOS model and simulation provides an effective way to enhance the device stability while retaining a relatively high mobility, which makes the corresponding devices suitable for ultradefinition, large-area, and high-frame-rate display applications.