Evgeny Pikhay

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 μm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the “5-cent RFID tag” become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 μW, which is sufficiently supplied by the on-chip energy harvesting unit.

A low-cost low-power non-volatile memory for RFID applications

One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18µm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8µW during operation cycles.

Radiation-hardened techniques for CMOS flash ADC

This work presents a rad-hard 4-bit 10MHz Flash ADC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels. The design takes into account the different effects of the radiation that could damage the circuits in harsh environments. The ADC has been integrated in a standard CMOS 0.18-μm technology by TowerJazz. The prototype has been tested with a custom methodology and showed a Total Dose immunity up to 300krad.

Non volatile memory for FPGA booting in space

This paper proposes a new non-volatile memory (NVM) architecture that would increase the radiation hardness of standard design. The memory allows storing the configuration bit-stream for on-satellites FPGAs reducing the necessity of information exchange with ground control to recover the system. A 1Mbit non-volatile memory prototype has been fabricated using a standard 180nm CMOS process using a Tower Semiconductors proprietary S-Flash cell.

Characterization of Single Poly Radiation Sensors

This letter reports on the mechanisms responsible for the operation of the original radiation sensor based on the floating gate (FG) principle. In contrast to known FG radiation sensors, the suggested device employs the CMOS inverter readout scheme and is implemented in a standard CMOS technology without additional masks. Single poly-FG sensor was charged both to positive and negative potentials and exposed to different types of radiation (Gamma-rays, X-rays, and UV). It is shown that the discharge is dominated by electrons activated from the FG and Si substrate. In contrast with other FG radiation sensors, the demonstrated device operates with zero voltage at the control gate. This allows significantly reduced power consumption and improved noise performance.

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

This work presents an innovative architecture to fabricate a non volatile memory for space applications using a S-Flash memory cell. The design takes into account the different effects of the radiation that could damage the circuits and the memory cell in harsh environments. The memory cell has been developed by TowerJazz Semiconductors to be compatible with the standard 180nm CMOS process. A 1Mbit prototype has been designed using the presented architecture.

Degradation study of single poly radiation sensors by monitoring charge trapping

Abstract Special test structures emulating the performance of C-sensor, a direct floating gate (FG) ionizing radiation sensor, were used to investigate its degradation under Gamma radiation. Original MOS transistors with bulks made of crystalline silicon and Poly allowed minimizing the number of irradiations required to study the peculiarities of charge accumulation in the dielectrics of C-sensors. Electrical characterization of the developed structures before and after the exposure to different doses of Gamma radiation was performed. The guidelines for improving sensor immunity to radiation degradation are discussed.

A GIDL free tunneling gate driver for a low power non-volatile memory array

A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low power low cost option for embedded RFID design. This cell requires the application of a 10V potential difference between the cells control lines for program and erase operations. Providing the required voltages includes several challenges in the design of the voltage driver, such as the elimination of Gate Induced Drain Leakage (GIDL) currents. In this paper, we present a voltage driver architecture that utilizes novel techniques to overcome the power consumption problems during high voltage propagation. This driver was implemented in the TowerJazz 0.18μm CMOS technology, providing the required functionality with a low static-power figure of 34.6pW.

Radiation sensor based on a floating gate device

Ionizing radiation sensor based on the nonvolatile floating gate (FG) C-Flash memory is demonstrated. The sensing is based on measuring the threshold voltage (Vt) shift of the modified C-Flash cell pre-charged by electrons or holes. The accumulated absorbed dose is calculated from the Vt shift of the memory cell after the exposure to radiation. The developed sensor is a candidate for embedding into passive RFID radiation measuring systems. It features ultra-low power operation and does not require power supply during the exposure sessions. The feasibility results for stand-alone sensors and 2kbit test arrays are presented and discussed in view of possible applications.

Re-usable 180nm CMOS dosimeter based on a floating gate device

A rad-hard monolithic dosimeter has been designed and simulated in a standard 180 nm CMOS technology. The radiation sensor (C-sensor) is based on a floating gate MOS discharge principle. The output current is processed by a current-to-voltage (I-to-V) interface and then converted by a 5-bit flash ADC. The dosimeter is re-usable (FG is recharged) and in this first version can detect a dose up to 1krad(Si) with a resolution of 30rad(Si), over process and temperature variations (0 to 85°C). The ADC allows easy further signal processing for calibration, averaging, etc. The power consumption of C-sensor plus I-to-V interface is less than 2mW from a single 5 V power supply, while the ADC consumes 160mW. The overall layout area is less than 0.25mm2. The Radiation Hardened By Design (RHBD) approach guarantees that the absorbed dose does not modify the performance of the mixed-signal circuitry.