Vladislav Dayan

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 μm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the “5-cent RFID tag” become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 μW, which is sufficiently supplied by the on-chip energy harvesting unit.

A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory

The realization of a low-cost passive radio frequency identification (RFID) tag requires the ability to fabricate the system in a bulk CMOS process without any additional process steps. A recently presented single-poly C-Flash memory bitcell provides an ultralow-power option for implementation of a nonvolatile memory array for use in an RFID system, using only core masks. This cell requires the application of a 10-V potential difference between the cells control lines for program and erase operations. Providing the required voltages, while using only standard devices results in several design challenges for the voltage drivers, such as the elimination of gate-induced drain leakage (GIDL) currents. In this paper, we present a pair of voltage driver architectures that utilize novel techniques to overcome these challenges. In addition, for the first time, we present an in-depth analysis of the dynamic behavior of standard level shifters. This analysis is applied to our proposed GIDL-free level shifters to provide a sizing methodology for optimization of the area, energy-per-operation, and delay of these circuits. The drivers were designed and fabricated in a TowerJazz 0.18- μm bulk CMOS technology, providing the required functionality with a low static-power figure of 47-49 pW and 0.03-0.36 pJ energy-per-operation.

A low-cost low-power non-volatile memory for RFID applications

One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18µm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8µW during operation cycles.

High Density MTP Logic NVM for Power Management Applications

We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.

Non volatile memory for FPGA booting in space

This paper proposes a new non-volatile memory (NVM) architecture that would increase the radiation hardness of standard design. The memory allows storing the configuration bit-stream for on-satellites FPGAs reducing the necessity of information exchange with ground control to recover the system. A 1Mbit non-volatile memory prototype has been fabricated using a standard 180nm CMOS process using a Tower Semiconductors proprietary S-Flash cell.

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

This work presents an innovative architecture to fabricate a non volatile memory for space applications using a S-Flash memory cell. The design takes into account the different effects of the radiation that could damage the circuits and the memory cell in harsh environments. The memory cell has been developed by TowerJazz Semiconductors to be compatible with the standard 180nm CMOS process. A 1Mbit prototype has been designed using the presented architecture.

A GIDL free tunneling gate driver for a low power non-volatile memory array

A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low power low cost option for embedded RFID design. This cell requires the application of a 10V potential difference between the cells control lines for program and erase operations. Providing the required voltages includes several challenges in the design of the voltage driver, such as the elimination of Gate Induced Drain Leakage (GIDL) currents. In this paper, we present a voltage driver architecture that utilizes novel techniques to overcome the power consumption problems during high voltage propagation. This driver was implemented in the TowerJazz 0.18μm CMOS technology, providing the required functionality with a low static-power figure of 34.6pW.