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Dive into the research topics where Evren Cesur is active.

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Featured researches published by Evren Cesur.


IEEE Transactions on Circuits and Systems | 2015

Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

Nerhun Yildiz; Evren Cesur; Kamer Kayaer; Vedat Tavsanoglu; Murathan Alpay

In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 × 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.


IEEE Transactions on Circuits and Systems Ii-express Briefs | 2012

On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters

Evren Cesur; Nerhun Yildiz; Vedat Tavsanoglu

In this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. The proposed architecture is suitable for real-time applications with high pixel rates. The prototype is capable of processing video streams up to a pixel rate of 373.2 megapixels per second (MP/s), including full-high-definition (HD) 1080p@60 (1080 × 1920 resolution, 60-Hz frame rate, and 124.4-MP/s visible pixel rate). This brief also contains convergence rate analysis results, along with some discussions on FIR and CNN-based implementation methods.


2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010) | 2010

A new control structure for the pipelined CNN processor arrays

Nerhun Yildiz; Evren Cesur; Vedat Tavsanoglu

In this paper an improvement over the control structure of the processor architecture reported in is proposed. Each processor in the array was controlled by the central control unit which proved to have some setbacks. These are: 1) the complexity of the control logic which tends to be more complicated as the number of processors gets higher; 2) the necessity to redesign the control logic for any change of the processor count in the array; 3) the problems in testability and reliability of each complex new design. Here we introduce an asynchronous control structure that eliminates problems relating to complexity, reusability and reliability.


european conference on circuit theory and design | 2013

Realization of preprocessing blocks of CNN based CASA system on FPGA

O. Levent Savkay; Nerhun Yildiz; Evren Cesur; Mustak E. Yalcin; Vedat Tavsanoglu

In this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. For future work, the post-processing part of the CASA system is proposed to be implemented on the same FPGA device as software, using either a soft or hard processor core. By the integration of the pre- and post-processing parts, the designed CASA system will be capable of processing full-HD 1080p@60 (1080×1920) video images in real-time.


signal processing and communications applications conference | 2016

Low power Internet of Things gateway

Tevfik Kadioglu; Nerhun Yildiz; Evren Cesur

In this paper, the hardware and software development of a gateway targeting Internet of Things applications is disclosed and a new UDP based sensor network communication model for the reduction of network traffic and power consumption is proposed. On the other hand, various information about Internet of Things, wireless sensor networks and Contiki operating system are also given throughout the paper.


signal processing and communications applications conference | 2015

Computer assisted sperm analysis system designed on a hybrid CPU + FPGA architecture

Osman Levent Savkay; Vedat Tavsanoglu; Mustak E. Yalcin; Evren Cesur

In this paper a Computer Assisted Semen Analysis (CASA) system designed on a hybrid CPU + FPGA hardware platform is presented. Multiple moving object tracking technique is used for spermatozoa motility analysis and an algorithm consisting of compositely applied various image processing techniques is used for spermatozoa morphology analysis. The parallel processing architecture of FPGAs are utilized for the image and video processing functions that our system use where high speed processing power is required. Various calculations are done on CPU by utilizing developed software. Our system incorporates also an HD digital camera which is mounted on a biological microscope. It has also been foreseen that our system will be a standalone intelligence system and flexibly programmable for different jobs.


international symposium on circuits and systems | 2014

Realization of processing blocks of CNN based CASA system on CPU and FPGA

O. Levent Savkay; Evren Cesur; Nerhun Yildiz; Mustak E. Yalcin; Vedat Tavsanoglu

In this paper, hardware optimization of the preprocessing and software implementation of the processing blocks of a computer-aided semen analysis (CASA) system are proposed, which is also implemented on an FPGA and ARM device as a working prototype. The software implementation of the track initialization, track maintenance, data validation and classification blocks of the processing part are implemented on a Zynq7000 ARM Cortex-A9 processor. In the preprocessing part, a real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. The CASA system introduced in this paper is capable of processing full-HD 1080p@60 (1080 × 1920) video images in real-time.


Cellular Nanoscale Networks and their Applications (CNNA), 2014 14th International Workshop on | 2014

Design of a third generation Real-Time Cellular Neural Network emulator

Nerhun Yildiz; Evren Cesur; Vedat Tavsanoglu

In this paper, the features of the next generation Real-Time Cellular Neural Network Processor (RTCNNP-v3) are discussed. The RTCNNP-v2 structure is the only CNN implementation that is reported to be capable of processing full-HD 1080p@60 (1920×1080 resolution at 60 Hz frame rate) video images in real-time, due to its fully-pipelined architecture, however, it has some weaknesses like the inability to divide the processing in spatial domain, record and recall intermediate results to an external memory and has some issues in its internal memory coding. Those shortcomings are to be addressed in the next design of our CNN emulator - RTCNNP-v3, which will increase the range of applications and enable the implementation to match the requirements of the cutting-edge movie production technologies like UHD (4K) and the future FUHD (8K).


Cellular Nanoscale Networks and their Applications (CNNA), 2014 14th International Workshop on | 2014

Sperm Morphology Analysis with CNN based algorithms

O. Levent Savkay; Evren Cesur; Mustak E. Yalcin; Vedat Tavsanoglu

In this paper Morphological Analysis part of our proposed computer-aided sperm analysis system (CASA) is simulated and the results beside the algorithm steps are presented. The morphology analysis is simply dealing with shape of the sperms and extracting the shape characteristics in medical parameters. The characteristics are obtained by image processing algorithms which utilizes Cellular Nanoscale Network (CNN) based and spatial image processing blocks. The following calculation of medical parameters are obtained from the outputs of image processing blocks. The algorithm is so designed to adapt the final SoC architecture such as Xilinx Zynq7000 device.


signal processing and communications applications conference | 2013

Handwritten character recognition application by using Cellular Neural Network

Nurullah Çalik; Evren Cesur; Vedat Tavsanoglu

Hand-written character recognition is one of the important fields of pattern recognition. Within the scope of this area of important documents and archives and other written texts transfering to digital media or recognition of the printer tries to unravel the problems. Many algorithms have been developed for these problems. Algorithms that have been developed to be desired, the high accuracy rate and being applicable for numeric desings like FPGA. Therefore, for classification, feature vector is extracted by using Gabor-like Cellular Neural Network (HSA) filters. These filters are implemented with efficient algorithms on FPGA [10]. By this means, an algorithm has been developed FIR filters designed by the Gabor more efficient in terms of processing time and accuracy, the percentage of capital letters, which at around 80%.

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Nerhun Yildiz

Yıldız Technical University

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Mustak E. Yalcin

Istanbul Technical University

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O. Levent Savkay

Istanbul Technical University

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Nurullah Çalik

Yıldız Technical University

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Oguzhan Yavuz

Yıldız Technical University

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Ramazan Cetin

Yıldız Technical University

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Umut Engin Ayten

Yıldız Technical University

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