Nerhun Yildiz

Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 × 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.

On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters

In this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. The proposed architecture is suitable for real-time applications with high pixel rates. The prototype is capable of processing video streams up to a pixel rate of 373.2 megapixels per second (MP/s), including full-high-definition (HD) 1080p@60 (1080 × 1920 resolution, 60-Hz frame rate, and 124.4-MP/s visible pixel rate). This brief also contains convergence rate analysis results, along with some discussions on FIR and CNN-based implementation methods.

A new control structure for the pipelined CNN processor arrays

In this paper an improvement over the control structure of the processor architecture reported in is proposed. Each processor in the array was controlled by the central control unit which proved to have some setbacks. These are: 1) the complexity of the control logic which tends to be more complicated as the number of processors gets higher; 2) the necessity to redesign the control logic for any change of the processor count in the array; 3) the problems in testability and reliability of each complex new design. Here we introduce an asynchronous control structure that eliminates problems relating to complexity, reusability and reliability.

Demonstration of the Second Generation Real-Time Cellular Neural Network Processor: RTCNNP-v2

This proceeding is compiled from our previous works, where architecture of the Second-Generation Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) was proposed. The system is designed for applications where high-resolution and high-speed is desired. The structure is fully-pipelined and the processing is real-time. Proposed structure is coded in VHDL and realized on two FPGA devices: one high-end and one low-budget. The system is the only reported CNN implementation supporting real-time Full-HD video image processing, to date.

Realization of preprocessing blocks of CNN based CASA system on FPGA

In this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. For future work, the post-processing part of the CASA system is proposed to be implemented on the same FPGA device as software, using either a soft or hard processor core. By the integration of the pre- and post-processing parts, the designed CASA system will be capable of processing full-HD 1080p@60 (1080×1920) video images in real-time.

An improved FPGA implementation of CNN Gabor-type filters

In this paper, a new Cellular Neural Network (CNN) structure for implementing two dimensional Gabor-type filters is proposed over our previous design. The structure is coded in VHDL and realized on a state of the art Altera Stratix IV 230 FPGA. The prototype supports Full-HD 1080p resolution and 60 Hz frame rate. One dedicated processor is used for each Euler iteration, where time step is taken as the same as optimum step size, and 50 iterations are implemented. The input/output, control, RAM and communication blocks of the realization are taken from our second generation real time CNN emulator (RTCNNP-v2).

Low power Internet of Things gateway

In this paper, the hardware and software development of a gateway targeting Internet of Things applications is disclosed and a new UDP based sensor network communication model for the reduction of network traffic and power consumption is proposed. On the other hand, various information about Internet of Things, wireless sensor networks and Contiki operating system are also given throughout the paper.

Realization of processing blocks of CNN based CASA system on CPU and FPGA

In this paper, hardware optimization of the preprocessing and software implementation of the processing blocks of a computer-aided semen analysis (CASA) system are proposed, which is also implemented on an FPGA and ARM device as a working prototype. The software implementation of the track initialization, track maintenance, data validation and classification blocks of the processing part are implemented on a Zynq7000 ARM Cortex-A9 processor. In the preprocessing part, a real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. The CASA system introduced in this paper is capable of processing full-HD 1080p@60 (1080 × 1920) video images in real-time.

Design of a third generation Real-Time Cellular Neural Network emulator

In this paper, the features of the next generation Real-Time Cellular Neural Network Processor (RTCNNP-v3) are discussed. The RTCNNP-v2 structure is the only CNN implementation that is reported to be capable of processing full-HD 1080p@60 (1920×1080 resolution at 60 Hz frame rate) video images in real-time, due to its fully-pipelined architecture, however, it has some weaknesses like the inability to divide the processing in spatial domain, record and recall intermediate results to an external memory and has some issues in its internal memory coding. Those shortcomings are to be addressed in the next design of our CNN emulator - RTCNNP-v3, which will increase the range of applications and enable the implementation to match the requirements of the cutting-edge movie production technologies like UHD (4K) and the future FUHD (8K).

Design of an Automatic Target Recognation algorithm

In this study, first, an Automated Target Recognition/Tracking (ATR, ATT) system is analyzed, developed and simulated on Matlab environment. Second, a new edge detection method is proposed which is obtained by combining two common edge detection algorithms. Finally, it is shown that Freeman chain codding can be used in feature extraction stage of an ATR system. The system is tested for many different image databases, except for its classification and decision making part, which is still under development, and the results are verified by human eye. Note that, with the development of the classification part, the results will be able to verified with an objective criteria. On the other hand, the designed ATR system is planed to be optimized for an hardware and implemented on an FPGA device in a future work.