Ewald Wachmann

Passivation integrity investigations for through wafer interconnects

Through wafer interconnects (TWI) with diameters greater than 50 mum have the advantage of extremely low contact resistances. The mechanics of the layers inside the TWI has to be well understood order to avoid passivation cracks. Results of simulation and mechanical investigations are discussed in this paper.

A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications

A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range from -40deg to 150deg C. A wider range, from -55deg to 180deg C, has been achieved in manufacturing. Full cell, and memory module functionality, and data retention of over 30 years for the automotive temperature range have been achieved. Write cycling of over 200K writes (tested up to 180degC) over the design temperature range has also been achieved. The memory cell and the technology are optimized to operate at very low voltage and consume very low power. The applications requiring high data retention (>50 years), over the industrial or automotive temperature range can be well served with this technology. The data confirms that this technology is a highly manufacturability and a reliable technology for the embedded non-volatile memory applications. The data presented is based on a 0.35mum CMOS technology implementation

Blue-Enhanced PIN Finger Photodiodes in a 0.35-

Finger photodiodes in PIN technology are introduced to enhance the responsivity for blue and ultraviolet light. A thick low doped epitaxial layer results in high responsivity and high bandwidth also for red and near-infrared light. Results of PIN finger photodiodes are compared to that of PIN photodiodes for 10- and 15-mum epitaxial intrinsic layer thickness. The cathode finger structure results in a high responsivity of 0.20 A/W (quantum efficiency 61%) for 410-nm light and a bandwidth of 1.25 GHz for 10- mum epi thickness at a reverse bias voltage of 3 V. The rise and fall times with an epitaxial layer thickness of 15 mum are below 1 ns for the wavelength range from 410 to 785 nm.

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SiGe-heterojunction bipolar transistors (HBTs) still sustain their leading RF-application position due to their good noise and HF properties. They also offer a relatively high operating voltage, which is limited by BVCEO, the emitter collector breakdown voltage with open base. We show that BVCER, the avalanche breakdown with a resistor RB connected to the base, can be used to define reliable operating conditions exceeding BVCEO. The measured BVCER data correlate very well with values calculated from basic transistor parameters and their corresponding multiplication factor data. The functionality of this concept is verified by investigating a power amplifier circuit used at emitter collector voltages exceeding BV CEO in operational mode enabling significant higher output power

SiGe BiCMOS Technology

Silicon photonics have generated an increasing interest in the recent year, mainly for optical telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside a high performance chip. In order to build a Opto-Electronic Integrated circuit (OEIC), a large European project HELIOS has been launched two years ago. The objective is to combine a photonic layer with a CMOS circuit by different innovative means, using microelectronics fabrication processes. High performance generic building blocks that can be used for a broad range of applications are developed such as WDM sources by III-V/Si heterogeneous integration, fast Si modulators and Ge or InGaAs detectors, Si passive circuits and specific packaging. Different scenari for integrating photonic with an electronic chip and the recent advances on the building blocks of the Helios project are presented.

BV CER - Increased Operating Voltage for SiGe HBTs

This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical interpretations are suggested.

HELIOS: pHotonics ELectronics functional Integration on CMOS

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

Evidence of erratic behaviors in p-channel floating gate memories and a cell architectural solution

Through Silicon Via (TSV) technology, to serve as electrical connection between metallization layers on the front and backside of the same wafer, has been developed by austriamicrosystems AG. During the development phase, defects were found that could be assigned to an established defect type known as “contact liner volcano”. To our knowledge this is the first time that such a volcano formation is reported from the inside of a TSV.

TCAD study of Single Photon Avalanche Diode on 0.35μm high voltage technology

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

Volcano effect in open through silicon via (TSV) technology

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices and pulse oximeters for medical applications. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process allows device miniaturization in addition to enhance its properties lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The dark current is studied, analyzed and measured for two different starting materials and for different geometries. A model previously proposed is reviewed and compared with experimental data.