Jordi Teva

Through Silicon Via (TSV) defect investigations using lateral emission microscopy

Abstract Infra-red photoemission microscopy has been applied for the localization of defects in 3D integrated circuits containing Through Silicon Vias (TSVs). For these investigations, the familiar (planar) emission microscopy configuration was extended to allow imaging and emission microscopy on vertical TSV sidewalls, from versatile 3D viewpoints. Flexible viewing orientation was achieved by introducing an additional reflecting surface into the optical path. Precise alignment of the angle of incidence at the air–silicon interface, with sufficient accuracy to ensure no problematic refraction-related errors, was possible using this experimental set-up. Three examples are presented, showing defect localizations and underlying physical leakage mechanisms in TSV structures.

Modeling the Growth of Tin Dioxide Using Spray Pyrolysis Deposition for Gas Sensor Applications

In order for the gas sensor devices to enjoy the miniaturization trend that has consumed much of the electronic device industry, major research in the field is undertaken. The bulky sensor devices of previous generations can not easily be incorporated into a CMOS processing sequence, because of their bulky nature and potential higher cost of production. More recently, materials such as zinc oxide and tin dioxide have shown powerful gas sensing capabilities. Among many potential deposition methods, spray pyrolysis has become a popular approach because of its ease of use and cost effectiveness. A model for spray pyrolysis deposition is developed and implemented within the level set framework. The implementation allows for a smooth integration of multiple processing steps for the manufacture of smart gas sensor devices. From the observations, it was noted that spray pyrolysis deposition, when performed with a gas pressure nozzle, results in good step coverage, analogous to a CVD process. This is mainly due to the atomizing nozzle being placed at a reasonable distance away from the wafer surface and reducing the droplets volume and mass in order to ensure they fully evaporate prior to contact with the substrate surface. A topography simulator for this deposition methodology is presented.

Modeling and Analysis of Spray Pyrolysis Deposited SnO2 Films for Gas Sensors

Metal oxide materials such as tin oxide (SnO2) show powerful gas sensing capabilities. Recently, the deposition of a thin tin oxide film at the backend of a CMOS processing sequence has enabled the manufacture of modern gas sensors. Among several potential deposition methods for SnO2, spray pyrolysis deposition has proven itself to be relatively easy to use and cost effective while providing excellent surface coverage on step structures and etched holes. A model for spray pyrolysis deposition using a pressure atomizer is presented and implemented in a Level Set framework. A simulation of tin oxide deposition is performed on a typical gas sensor geometry and the resulting structure is imported into a finite element tool in order to analyze the electrical characteristics and thermo-mechanical stress present in the grown layer after processing. The deposition is performed at 400 °C and the subsequent cooling to room temperatures causes a stress to develop at the material interfaces due to variations in the coefficient of thermal expansion between the different materials.

Modeling the growth of thin SnO2 films using spray pyrolysis deposition

The deposition of a thin tin oxide film allows for the manufacture of modern gas sensors to replace the bulky sensors of previous generations. Spray pyrolysis deposition is used to grow the required sensing thin films, as it can be seamlessly integrated into a standard CMOS processing sequence. A model for spray pyrolysis deposition is developed and implemented within the Level Set framework. The implementation allows for a seamless integration of multiple processing steps for the manufacture of smart gas sensor devices. From observations it was noted that spray pyrolysis deposition, when performed with a gas pressure nozzle, results in good step coverage, analogous to a CVD process. This is due to the liquid droplets evaporating prior to contact with the heated wafer surface and subsequently depositing on top of the exposed silicon in vapor form.

Metal oxide nanowire gas sensors for indoor and outdoor environmental monitoring

We present performance results of SnO2 and CuO nanowire gas sensor devices, where single and multi-nanowire device configurations have been employed in order to optimize sensor design. In particular the response to the target gases CO, H2, and H2S has been measured in dry and humid air; both the SnO2 and CuO nanowire sensors are able to detect CO in the low ppm concentration range, which is important for environmental monitoring. The CuO multi-nanowire devices show an extraordinary high response to H2S with sensitivity in the low ppb concentration. We present our developments of CMOS technology based micro-hotplates, which are employed as platform for gas sensitive thin films and nanowires. Potential heterogeneous integration of nanowires on the micro-hotplate chips as well as an approach towards gas sensor arrays is discussed. We conclude that CMOS integrated multi-nanowire gas sensors are highly promising candidates for the practical realization of multi-parameter sensor devices for indoor and outdoor environmental monitoring.

TCAD study of Single Photon Avalanche Diode on 0.35μm high voltage technology

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

New integration concept of PIN photodiodes in 0.35μm CMOS technologies

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

Dark current study for CMOS fully integrated-PIN-photodiodes

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices and pulse oximeters for medical applications. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process allows device miniaturization in addition to enhance its properties lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The dark current is studied, analyzed and measured for two different starting materials and for different geometries. A model previously proposed is reviewed and compared with experimental data.

Characterization of spectral optical responsivity of Si-photodiode junction combinations available in a 0.35μm HV-CMOS technology

The 0.35μm HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7μm depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.

Gathering effect on dark current for CMOS fully integrated-, PIN-photodiodes

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices, and pulse oximeters. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process flow opens the window to device miniaturization enhancing its properties and lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity float zone substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The photodiodes in the array are isolated by a guard ring consisting of a n+-p+ diffusions. However, the introduction of the guard ring design, necessary for photodiode-to-photodiode isolation, leads to an increase of the photodiodes dark current. In this article, the new parasitic term on the dark current is identified, formulated, modelled and experimental proven and has finally been used for an accurate design of the guard ring.