F. Allibert

Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization

It has been reported previously [N. Bresson et al., Proceedings of the ECS Seventh International Symposium on Silicon-on-Insulator Technology and Devices, 2005 (unpublished), pp. 317–324; F Allibert et al., Proceedings of the IEEE International SOI Conference, Honolulu, HI, 2002 (unpublished)] that the film thickness strongly impacts the parameters extracted using the pseudo metal oxide semiconductor field effect transistor (pseudo-MOSFET) with the usual FET equations [S. Cristoloveanu and S. S. Li, Electrical Characterization of SOI Materials and Devices (Kluwer, Boston, MA, 1995)]. In this paper, we investigate the influence of top free-surface states on the pseudo-MOSFET characteristics by comparing passivated versus nonpassivated samples. The parameters of concern, investigated here, are carrier mobility, density of interface states, threshold (VT), and flatband (VFB) voltages. Based on systematic measurements and existing models [H. J. Hovel, Solid-State Electron. 47, 1311 (2003)] for VT, VFB, and su...

Germanium-On-Insulator (GeOI) structure realized by the Smart Cut™ technology

First results on formation of thin film GeOI structures by the Smart Cut™ technology are presented in this paper. Thin single crystal layers of Ge have been successfully transferred, via oxide bonding layer, onto standard Si substrates with diameters ranging from 100 to 200 mm. Compared to SOI manufacturing, the development of GeOI requires adaptation to the available germanium material, since the starting material can be either bulk Ge or an epitaxial layer. Some results will be presented for GeOI formation according to the different technological options. Germanium splitting kinetics will be discussed and compared to already published results. To show good quality of the GeOI structures, detailed characterization has been done by TEM cross sections for defect densities, interfaces abruptness and layers homogeneities evaluation. AFM was used for surface roughness measurements. These results help define procedures that are required to achieve large diameter high quality GeOI structures.

Internal Dissolution of Buried Oxide in SOI Wafers

High temperature anneal of SOI wafers in oxygen-free atmosphere results in internal buried oxide dissolution and top Si layer etching. Dissolution rate is determined by interstitial oxygen diffusion through the top Si layer and evaporation from the top Si surface in the form of SiO. It has been observed that kinetics of the process follows linear-parabolic law. Simple thermodynamic model is proposed, which explains observed dependences on temperature and top Si layer thickness.

From SOI materials to innovative devices

Abstract Novel device architectures and materials are required to extend the limits of ULSI microelectronics. Recent properties of UNIBOND ® and SOS substrates, determined with the pseudo-MOSFET technique are described. The discussion of advanced SOI devices includes two basic aspects: the scaling of conventional MOSFETs and the design of alternative structures. We discuss the effects resulting from the reduction in channel width, length and thickness and present the merits of more innovative transistors with ground-plane, dynamic-threshold or double-gate.

Double-Gate MOSFETs: Is Gate Alignment Mandatory?

Double-gate (DG) MOSFETs promise to enhance transistor capabilities beyond the limits of conventional CMOS technology. In this paper, we study for the first time the impact of gate misalignment in “non-ideal” DG devices that may be much easier to fabricate than self-aligned versions. Drain current, transconductance, series resistance effects, subthreshold slope and carrier concentration profiles are simulated for different architectures, based on a 50nm long SOI MOSFET. We compare single gate, ideal aligned DG, and non-aligned DG transistors in which unequal gate lengths are used to compensate for the gate misalignment. We find that non-aligned DG devices are competitive with and even, in some cases, superior to ideal DG MOS, albeit with unusual gm curves.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.

Germanium oxynitride (GeOxNy) as a back interface passivation layer for Germanium-on-insulator substrates

This paper describes the development of a GeOxNy surface passivation of germanium, which is mandatory for microelectronics germanium-on-insulator (GeOI) substrate fabrication. Indeed, germanium surface reactivity in ambient atmosphere requires the development of Ge surface passivation in order to provide an electrically acceptable interface between the active layer and the buried oxide (BOX) of GeOI substrates. In this paper, GeOI substrates with a passivation interlayer between the Ge film and the BOX were fabricated using the Smart Cut™ technology. Plasma treatments produced a germanium oxynitride (GeOxNy) passivation interlayer with a nitrogen concentration up to 40% and thickness of 3nm. Electrical activity in such GeOI active layer was investigated with pseudo-metal-oxide-semiconductor field effect transistor measurements. Electron mobility reaches a value of 670cm2V−1s−1, notably higher than those typically reported on nonpassivated GeOI structures.

Hole Transport in Strained and Relaxed SiGe Channel Extremely Thin SOI MOSFETs

We report experimental data comparing aggressively scaled SiGe channel extremely thin SOI MOSFETs with either relaxed or strained channels. The analysis clearly demonstrates that without strain, SiGe channel delivers performance comparable with relaxed Si devices. Significantly higher performance is observed only in compressively strained SiGe channel devices, especially in narrower devices where the transverse component of the strain is partially relaxed.

Germanium-on-insulator (GeOI) structures realized by the Smart Cut/spl trade/ technology

This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin single crystal layers of Ge [001] have been successfully transferred via oxide to oxide bonding or by Ge to oxide bonding, onto 100 mm and 200 mm Si substrates. The surface roughness of the wafers has been measured by AFM. The surface roughness originating from the splitting step is eliminated by a soft polishing step using a CMP.

Double-gate MOSFETs: performance and technology options

The advantages of double-gate (DG) SOI MOSFETs over conventional, single-gate transistors are described in terms of performance and potential for ultimate scaling. The peculiarity of DG-MOSFETs is that the top and bottom gates are biased simultaneously to establish equal surface potentials: V/sub G2/ = V/sub G1/ for identical gate oxides, or V/sub G2/ = V/sub G1/(t/sub 0X2//t/sub 0X1/) to compensate for the difference in front and back oxide thickness. In fully depleted transistors with a thin enough film, controlling the channel from both sides, forces most of the carriers to flow in the middle of the film, according to the volume inversion concept. Volume inversion results in excellent properties, which will be reviewed in this paper. In particular, the carrier mobility is enhanced, so that the transconductance in double-gate mode exceeds twice the value observed in single-gate mode. A DGMOSFET is more than the sum of two classical transistors.