Carlos Mazure

Ferroelectric strontium bismuth tantalate thin films deposited by metalorganic chemical vapour deposition (MOCVD)

Thin films of Sr 1-x Bi 2+x Ta 2 O 9 (SBT) have been deposited by metalorganic chemical vapor deposition (MOCVD) on 150 mm Si wafers with Pt/Ti electrodes. The choice of Bi precursor significantly affects the process; film homogeneity is significantly improved when using a β-diketonate Bi precursor in combination with compatible Sr and Ta precursors. A highly repeatable process has been developed, with good run-to-run composition and thickness control. Effects of Bi volatility have been investigated in annealing experiments that show the onset of Bi loss at ∼570°C at reduced pressure (1-10 Torr). Film properties relevant to integrated ferroelectric random access (Fe RAMS) memories have also been characterized. Remenant polarizations (2P r ) up to 24 μC cm -2 have been obtained at 5 V, with 90% saturation of 2P r at 1.5 V and a coercive voltage of 0.52 V for a 140 mn film. Electrical leakage current density values were < 2×10 -8 A cm -2 at 1.5 V. Fatigue endurance has been measured to 10 11 cycles with < 10% degradation in switched charge.

Influence of Ti-content in the bottom electrodes on the ferroelectric properties of SrBi2Ta2O9 (SBT)

Abstract Stress behavior, results of AES analysis and electrical properties of SBT in dependence of electrode structure and annealing conditions are discussed. Evidence for degradation of the electrical properties of SBT due to diffusion of Ti is presented.

Hot carrier hardness analysis of submicrometer LDD devices

A detailed analysis of the degradation of various lightly doped drain (LDD) devices is presented. Technology parameters that are varied are gate length, LDD n-dose, and energy for devices with 20-nm gate oxide. Different DC stress conditions are investigated. To gain insight into the degradation process a simulation tool is used that self-consistently calculates the oxide damage during a DC stress experiment. This enables the location and amount of oxide charges and interface states due to hot carrier injection to be obtained. The relationship between stress-induced damage and device hot carrier hardness is discussed. >

Properties of SrBi2Ta2O9 thin films grown by MOCVD for high density FeRAM applications

Abstract A novel low temperature MOCVD process for SrBi2Ta2O9 (SBT) thin films is described. The process, which uses Bi(thd)3 as the Bi source, allows deposition temperatures down to 300°C enabling to maintain the integrity of the Pt bottom electrode. Excellent run-to-run repeatability and a step coverage > 90% on a 0.5 μm structure have been demonstrated. After annealing at 800°C, 140 nm thick films showed remanent polarizations of 2Pr = 25 μC/cm2 @ 5V and leakage currents between 10-8-10-9 A/cm2 @ 3 V. Endurance after 2x1011 cycles was 90% using a 1.8 V, 1MHz square pulse signal. This manufacturable CVD process removes a further obstacle for production of high density ferroelectric memories (16M and above).

Improvement of latchup hardness by geometry and technology tuning

A latchup characterization method for CMOS technologies is presented. By separating the role of the parasitic bipolar transistors and the well and substrate shunt efficiencies, the interplay of geometry and technology becomes evident. An optimization of the device latchup hardness is achieved by partitioning the n/sup +/-p/sup +/ spacing with respect to the well. Substrate trigger currents depend on technological features such as substrate doping, well doping, and epilayer thickness. >

MOCVD of SrBi 2 Ta 2 O 9 for Integrated Ferroelectric Capacitors

SrBi 2 Ta 2 O 9 (SBT) is a promising material for ferroelectric random access memories (FERAMs) because it has high resistance to fatigue and imprint combined with low coercive field. Metalorganic chemical vapor deposition (MOCVD) offers the ability to produce high quality, conformai SBT films for both high and low density memory applications. An MOCVD process based on liquid delivery and flash vaporization has been developed which allows precise delivery of low vapor pressure precursors to the process. Precursor decomposition has been examined over a wide temperature range and the effects of process pressure have been examined. It is shown that Bi(thdb is superior to Bi(Ph) 3 as a source of Bi, offering a wide decomposition window with compatible Sr and Ta precursors so that a simple, well-controlled, and repeatable process is achieved at low temperatures. Films with 90% conformallity have been grown on 0.6 μm structures with a 1:1 aspect ratio. The MOCVD process yields the fluorite phase, which is transformed to the ferroelectric layered perovskite phase upon annealing in oxygen. Dielectric constants (e) of 200 and remanent polarization (2P r )up to 16 μC/cm 2 have been achieved on 150 mm wafers.

Influence of dry etching using argon on structural and electrical properties of crystalline and non-crystalline SrBi2Ta2O9 thin films

Abstract After patterning the Platinum/crystalline SrBi2Ta2O9 bilayer by Argon based Reactive Ion Etching (RIE), a degradation of the remanent polarization and leakage current of the capacitors for smaller feature sizes is observed. To simulate the study of the side wall of the capacitors, etching of blanket SBT is used as a model experiment. It is shown that etching of crystalline SBT is damaging the SBT material, resulting in the formation of small crystallites (SEM), the appearance of an unknown peak (XRD) and reduction of the Bismuth content on the SBT surface (AES). Using non-crystalline SBT, neither a degradation of electrical properties for smaller feature sizes nor a structural damage of blanket SBT is found after etching and recrystallization annealing although after etching of non-crystalline SBT also a loss of Bi is seen as indicated by AES. Therefore the following model is proposed: Patterning the Pt/crystalline SBT capacitor leads to a Bi deficient edge of the dielectric. Due to the crystalli...

Role of recovery anneals for chemical solution deposition (CSD) based SrBi2Ta2O9 (SBT) thin films

Abstract Using a recovery anneal after deposition of the Pt top electrode and patterning the Platinum / SrBi2Ta2O9 bilayer has been established to obtain well shaped hysteresis curves with low leakage currents. Electrical properties of SBT test capacitors in dependence of temperature and time for the recovery anneal are discussed. Evidence for degradation of the electrical properties of SBT capacitors after patterning due to the appearance of a new unknown peak in X-ray diffraction (XRD) is presented.

Technology challenges and solutions for 1Gbit and beyond

Abstract The need for higher DRAM densities, for cost effective manufacturing and the price pressure puts the DRAM development on a highly innovative path. The fast pace with which DRAM cell sizes are reduced results in many technology issues. This talk discusses the deep trench cell architecture, its advantages and the main technology innovations that have made the aggressive scaling of the DRAM cell possible. The issues related to Gbit DRAMs, the new challenges and potential innovations will be presented.

Advanced Simulation for Reliability Optimization of Submicron LDD MOSFETs

We present an advanced technique for optimization of source/drain structures of submicron MOSFETs with respect to hot carrier degradation. This technique is based on the simulation and analysis of the distribution of hot electrones and holes injected into the gate oxide obtained from a consistent, temperature-dependent gate and substrate current model. This method allows to judge the reliability performance of S/D Structures which the analysis of the electric fields fails to provide the necessary insight. The applicability of the method is demonstrated by comparison with experimental data from subμm-logic and 16M DRAM MOSFETs.