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Dive into the research topics where Yisuo Li is active.

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Featured researches published by Yisuo Li.


Journal of Nanotechnology | 2012

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Dim-Lee Kwong; Xianglin Li; Yuan Sun; G. Ramanathan; Zhixian Chen; She-Mein Wong; Yisuo Li; Nansheng Shen; Kavitha D. Buddharaju; Y. H. Yu; Sungjoo Lee; Navab Singh; G. Q. Lo

This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.


Archive | 2005

Semiconductor device layout and channeling implant process

Yisuo Li; Xiaohong Jiang; F. Benistant


Archive | 2010

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

Sanford Chu; Yisuo Li; Guowei Zhang; Purakh Raj Verma


Archive | 2004

LOW COST SOURCE DRAIN ELEVATION THROUGH POLY AMORPHIZING IMPLANT TECHNOLOGY

Yisuo Li; F. Benistant; Kian Meng Tee; King Jien Chui


Archive | 2013

Surround gate CMOS semiconductor device

Fujio Masuoka; Hiroki Nakamura; Shintaro Arai; Tomohiko Kudo; Y. Jiang; King-Jien Chui; Yisuo Li; Xiang Li; Zhixian Chen; Nansheng Shen; Vladimir Bliznetsov; Kavitha D. Buddharaju; Navab Singh


Archive | 2008

INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN

Guowei Zhang; Yisuo Li; Ming Li; Purakh Raj Verma; Shao-Fu Sanford Chu


Archive | 2004

Shallow low energy ion implantation into pad oxide for improving threshold voltage stability

Yisuo Li; F. Benistant; Kim Hyun Sik; Zhao Lun


Archive | 2011

SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE

Jeoung Mo Koo; Purakh Raj Verma; Sanford Chu; Chunlin Zhu; Yisuo Li


Archive | 2011

Surrounding gate transistor (SGT) structure

Fujio Masuoka; Hiroki Nakamura; Shintaro Arai; Tomohiko Kudo; King-Jien Chui; Yisuo Li; Y. Jiang; Xiang Li; Zhixian Chen; Nansheng Shen; Vladimir Bliznetsov; Kavitha D. Buddharaju; Navab Singh


Archive | 2004

Structure and method to form source and drain regions over doped depletion regions

King Jien Chui; F. Benistant; Ganesh Shamkar Samudra; Kian Meng Tee; Yisuo Li; Kum Woh Vincent Leong; Kheng Chok Tee

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F. Benistant

Chartered Semiconductor Manufacturing

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Purakh Raj Verma

Chartered Semiconductor Manufacturing

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Guowei Zhang

Chartered Semiconductor Manufacturing

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Kian Meng Tee

Chartered Semiconductor Manufacturing

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King Jien Chui

Chartered Semiconductor Manufacturing

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King-Jien Chui

National University of Singapore

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