F. Ciciriello

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Natale Demaria∗† INFN Sezione di Torino, Torino, Italy E-mail: demaria@to.infn.it F.Ciciriello, F.Corsi, C.Marzocca Politecnico di Bari, Bari, Italy G.De Robertis, F.Loddo, C.Tamma INFN Sezione di Bari, Bari, Italy V.Liberali, S.Shojaii, A.Stabile INFN Sezione di Milano and Universita degli Studi di Milano, Milano, Italy M.Bagatin, D.Bisello, S.Gerardin, S.Mattiazzo, L.Ding, P.Giubilato, A.Paccagnella INFN Sezione di Padova and Universita di Padova, Padova, Italy F.De Canio, L.Gaioni, M.Manghisoni, V.Re, G.Traversi, E.Riceputi INFN Sezione di Pavia and Universita di Bergamo, Bergamo, Italy L.Ratti, C.Vacchi INFN Sezione di Pavia and Universita di Pavia, Pavia, Italy R.Beccherle, G.Magazzu, F.Morsani, F.Palla INFN Sezione di Pisa, Pisa, Italy G.M.Bilei, M.Menichelli INFN Sezione di Perugia, Perugia, Italy E.Conti, S.Marconi, D.Passeri, P.Placidi INFN Sezione di Perugia and Department of Engineering, Universita di Perugia, Italy G.Dellacasa, G.Mazza, A.Rivetti, M.D.Da Rocha Rolo INFN Sezione di Torino, Torino, Italy E.Monteil, L.Pacher INFN Sezione di Torino and University of Torino, Torino, Italy

Interfacing a SiPM to a current-mode front-end: Effects of the coupling inductance

A current-mode approach is often used when designing front-end electronics for Silicon Photomultipliers, to cope with the peculiar features of this kind of detectors. Very low input resistance Rin and bandwidth BW as large as possible are classic design choices for the preamplifier, since it is commonly assumed that timing accuracy performance are optimized if this strategy is adopted. In our study, we show that this design approach leads to non-optimal results, due to the unavoidable presence of parasitic interconnection inductance between the detector and the front-end electronics. An approximate model, able to reproduce the behavior of the resulting circuit during the fast rising edge of the output pulse, has been employed to analyze the influence of the interconnection inductance on the slope of the signal. Thus, considering a typical current-mode preamplifier, based on a BJT current buffer, the existence of Rin-BW pairs which optimize the timing accuracy of the detection system has been demonstrated.

BASIC32_ADC, a front-end ASIC for SiPM detectors

BASIC32_ADC is the last version of a family of multichannel ASICs developed to read-out Silicon Photo-Multiplier detectors in medical imaging applications. With respect to the previous realizations, modifications of the analog channel structure and a different overall organization of the ASIC architecture have been adopted to solve problems which could arise when a continuous slab of scintillating crystal is read out by an array of photodetectors to extract the Depth Of Interaction (DOI) information. In fact, in this case, the detectors peripheral with respect to the center of interaction will receive a small amount of photons which do not pile up in effective way, thus producing probably a current pulse smaller than the threshold set to cut off the dark pulses. As a consequence, the related channels can be ignored in a sparse read-out acquisition, even though they are associated to a significant amount of charge. The self-triggered ASIC features 32 read-out channels, exhibits improved configuration flexibility and includes an 8-bit, two step subranging ADC. In this work we report on the design and the first characterization results of the ASIC.

TOT_AL: An ASIC for TOF and DOI measurement

We present the architecture of a new ASIC intended to read-out matrices of Silicon Photomultipliers coupled to continuous slabs of scintillating crystals for medical imaging applications. Time Of Flight (TOF) measurements, xy position and Depth Of Interaction (DOI) evaluation for the gamma photon require setting the detection threshold down to the level of one single photon and accurate estimation of the energy of the event. We propose a large bandwidth, current mode analog front-end able to discriminate valid events from the dark pulses generated by the SiPM on the basis of the charge contained in the detector signal. The LVDS output of the channel provides a rectangular pulse with a very fast leading edge, which marks the arrival of the event, and duration that is linearly related to the total charge generated by the detector, thus implementing a sort of Time over Threshold (ToT) technique. Thus, an external TDC can be used to extract both time and energy information. A 5 channel prototype ASIC, called TOT_AL, has been designed and the timing accuracy achieved in post-layout simulations is about 235ps FWHM, with single photo-electron resolution in the charge measurements. We describe the structure and the operating mode of the analog channel and the hardware solutions that have been exploited in order to reach the required specifications in terms of timing accuracy and linearity of the energy measurements.

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started.

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e− and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm2 and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm2. ENC value is below 100 e− for an input capacitance of 50 fF and in-time threshold below 1000 e−. Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DACs are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

TDC-based readout electronics for real-time acquisition of high resolution PET bio-images

Positron emission tomography (PET) is a clinical and research tool for in vivo metabolic imaging. The demand for better image quality entails continuous research to improve PET instrumentation. In clinical applications, PET image quality benefits from the time of flight (TOF) feature. Indeed, by measuring the photons arrival time on the detectors with a resolution less than 100 ps, the annihilation point can be estimated with centimeter resolution. This leads to better noise level, contrast and clarity of detail in the images either using analytical or iterative reconstruction algorithms. This work discusses a silicon photomultiplier (SiPM)-based magnetic-field compatible TOF-PET module with depth of interaction (DOI) correction. The detector features a 3D architecture with two tiles of SiPMs coupled to a single LYSO scintillator on both its faces. The real-time front-end electronics is based on a current-mode ASIC where a low input impedance, fast current buffer allows achieving the required time resolution. A pipelined time to digital converter (TDC) measures and digitizes the arrival time and the energy of the events with a timestamp of 100 ps and 400 ps, respectively. An FPGA clusters the data and evaluates the DOI, with a simulated z resolution of the PET image of 1.4 mm FWHM.