F. Conzatti

Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained.

Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs

We present a comparative study of the surfaceroughness (SR)-induced variability at low supply voltage VDD = 0.3 V in nanowire InAs tunnel FETs and strained-silicon (sSi) MOSFETs. By exploiting a 3-D full-quantum approach based on the Non-Equilibrium Greens Function formalism, we show that the Ion variability in InAs tunnel FETs is much smaller than the Ioff variability, whereas for VDD = 0.3 V, the sSi MOSFETs working in the subthreshold regime present similar Ion and Ioff variability. We explain the smaller Ion compared with Ioff variability of InAs tunnel FETs by noting that in the source depletion region, where tunneling mainly occurs for VGS = VDD, microscopic subband fluctuations induced by SR are small compared to macroscopic band bending due to the built-in potential of the source junction and to the gate bias. This results in SR-induced variability that is larger in InAs tunnel FETs than in sSi MOSFETs.

Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations

This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs.

A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs

This work investigates the strain engineering in InAs nanowire Tunnel-FETs. To this purpose we developed a simulator based on the NEGF formalism and employing an 8×8 k·p Hamiltonian. The model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the bandstructure. Elastic and inelastic phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in InAs Tunnel-FETs enable: (a) a remarkable enhancement of the I<inf>on</inf> with no significant degradation of the subthreshold slope (SS); (b) large improvements in the I<inf>off</inf> versus I<inf>on</inf> tradeoff for low I<inf>off</inf> and V<inf>DD</inf> values; (c) significant widening of I<inf>off</inf> and V<inf>DD</inf> window where Tunnel-FETs can compete with silicon MOSFETs.

Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs

This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel technique. A large vertical compressive strain is observed in FinFETs and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFETs lateral interfaces w.r.t. (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of the fin-width, fin-height and fin-length stress components on n- and p-FinFETs mobility and to identify optimal stress configurations.

Simulation study of the on-current improvements in Ge and sGe versus Si and sSi nano-MOSFETs

This paper employs a state-of-the-art semi-classical transport model for inversion layers to analyze the Ion in Si, sSi, Ge and sGe n- and p-MOSFETs by accounting for all the relevant scattering mechanisms (including the remote surface-optical phonons (SOph) and remote Coulomb scattering (remQ) related to high-κ dielectrics), in which strain is implicitly introduced by a modification of the band structure. Our models are first validated against experiments for both mobility and IDS in nanoscale transistors. Then the Ion in Ge and Si MOSFETs is compared for different crystal orientations and strain conditions.

On the Surface-Roughness Scattering in Biaxially Strained n- and p-MOS Transistors

Electron- and hole-mobility enhancements in biaxially strained metal-oxide-semiconductor transistors are still a matter for active investigation, and this brief presents a critical examination of a recently proposed interpretation of the experimental data, according to which the strain significantly modifies not only the root-mean-square value but also the correlation length of the surface-roughness spectrum. We present a systematic comparison between comprehensive numerical simulations and experiments, which supports such an interpretation.

Pseudo-spectral method for the modelling of quantization effects in nanoscale MOS transistors

This paper presents a systematic comparison between the numerical efficiency of the pseudo-spectral (PS) and finite difference (FD) methods for the solution of eigenvalue problems related to both n and p-MOS transistors, with different geometries and carrier dimensionalities. Our results indicate remarkable advantages of the PS compared to the FD method in terms of CPU time.

On the role of Coulomb scattering in hafnium-silicate gated silicon n and p-channel metal-oxide-semiconductor-field-effect-transistors

In this work, the impact of the local and remote Coulomb scattering mechanisms on electron and hole mobility are investigated. The effective mobilities in quasi-planar finFETs with TiN/Hf0.4Si0.6O/SiO2 gate stacks have been measured at 300 K and 4 K. At 300 K, electron mobility is degraded below that of bulk MOSFETs in the literature, whereas hole mobility is comparable. The 4 K electron and hole mobilities have been modeled in terms of ionized impurity, local Coulomb, remote Coulomb and local roughness scattering. An existing model for remote Coulomb scattering from a polycrystalline silicon gate has been adapted to model remote Coulomb scattering from a high-κ/SiO2 gate stack. Subsequently, remote charge densities of 8 × 1012 cm−2 at the Hf0.4Si0.6O/SiO2 interface were extracted and shown to be the dominant Coulomb scattering mechanism for both electron and hole mobilities at 4 K. Finally, a Monte Carlo simulation showed remote Coulomb scattering was responsible for the degraded 300 K electron mobility.

A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs

This paper reports a simulation study investigating the drive current in the prototypical SiGe n-type FinFET depicted in Fig.1 and for different values of the Ge content x in the Si(1-x)Gex active layer. To this purpose we performed strain simulations, band-structure calculations and Multi-Subband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer.