Pierpaolo Palestri

Electromechanical Piezoresistive Sensing in Suspended Graphene Membranes

Monolayer graphene exhibits exceptional electronic and mechanical properties, making it a very promising material for nanoelectromechanical devices. Here, we conclusively demonstrate the piezoresistive effect in graphene in a nanoelectromechanical membrane configuration that provides direct electrical readout of pressure to strain transduction. This makes it highly relevant for an important class of nanoelectromechanical system (NEMS) transducers. This demonstration is consistent with our simulations and previously reported gauge factors and simulation values. The membrane in our experiment acts as a strain gauge independent of crystallographic orientation and allows for aggressive size scalability. When compared with conventional pressure sensors, the sensors have orders of magnitude higher sensitivity per unit area.

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to the potential and calibrated scattering models are used to study electronic transport in bulk and double-gate silicon-on-insulator MOSFETs with L/sub G/ down to 14-nm designed according to the 2003 International Technology Roadmap for Semiconductors. Simulations with and without scattering are used to assess the influence of quasi-ballistic transport on the MOSFET on-current. We analyze in detail the flux of back-scattered carriers. The role of scattering in different parts of the device is clarified and the MC results are compared to simple models for quasi-ballistic transport presented in the literature.

Multisubband Monte Carlo Study of Transport, Quantization, and Electron-Gas Degeneration in Ultrathin SOI n-MOSFETs

This paper presents a new self-consistent multisubband Monte Carlo model for electronic transport in the inversion layer of decananometric MOSFETs. The simulator is 2D in real space and in k-space and accounts for the electron-gas degeneracy in the k-space. Simulation of nanoscale ultra-thin-body silicon-on-insulator MOSFETs shows that the subband structure and the carrier degeneracy strongly affect the transport properties and, in particular, the injection velocity and the channel back-scattering

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation

We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.

Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design.

Understanding quasi-ballistic transport in nano-MOSFETs: part II-Technology scaling along the ITRS

The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum-mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for L/sub G/ below approximately 50 nm and contributes most part of the I/sub ON/ improvements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.

Closed- and open-boundary models for gate-current calculation in n-MOSFETs

The gate current of different submicron MOS structures has been calculated using two different approaches to evaluate the eigenvalue energy and the escape-time of the quasi-bound states of the potential energy well at the Si/SiO/sub 2/ interface. The numerical issues involved in the implementation of these approaches (one semi-classical, the other quantum-mechanical) inside a device simulator are presented. Simulations performed on different thin-oxide MOS structures show that, compared to the quantum-mechanical treatment, the semi-classical approach is faster, numerically less demanding, and surprisingly accurate in estimating the escape-times. Nevertheless, differences in the eigenvalue energy computed assuming open or closed boundary-conditions at the system boundaries sensibly affect the predicted gate current values.

A Design Methodology for MOS Current-Mode Logic Frequency Dividers

In this work, a methodology for the design of MOS current-mode logic frequency dividers is presented. A mix of hand calculations and circuit simulations is used to relate the power consumption and the frequency of operation. Each latch in the dividers is sized separately in order to minimize the overall power consumption. Furthermore, the effect on the power consumption of circuit parameters such as output swing and voltage gain of the input differential pair is analyzed in detail. The methodology has been applied to dividers by two and dividers by three with 50% output duty cycle

On the Apparent Mobility in Nanometric n-MOSFETs

This letter investigates the definition and determination of mobility in nanometric metal-oxide-semiconductor transistors by means of multisubband Monte Carlo simulations. Our results clearly show that the transport in nano-MOSFETs, even for very small VDS, is far from being uniform and local. Consequently, the apparent mobility extracted from the experiments is a channel-length-dependent quantity, which is only partly related to the uniform transport mobility. Our study comprises both the electrical and magnetoresistance mobility.