L. Selmi

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to the potential and calibrated scattering models are used to study electronic transport in bulk and double-gate silicon-on-insulator MOSFETs with L/sub G/ down to 14-nm designed according to the 2003 International Technology Roadmap for Semiconductors. Simulations with and without scattering are used to assess the influence of quasi-ballistic transport on the MOSFET on-current. We analyze in detail the flux of back-scattered carriers. The role of scattering in different parts of the device is clarified and the MC results are compared to simple models for quasi-ballistic transport presented in the literature.

Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application

In this paper, we present a comprehensive experimental characterization of electron and hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n- and p-MOSFETs. Measurements have been performed at different temperatures using a special test structure able to circumvent parasitic resistance effects. Our results indicate that, at large inversion densities (N/sub inv/), the mobility of ultrathin SOI transistors is largely insensitive to silicon thickness (T/sub SI/) and is larger than in heavily doped bulk MOS because of a lower effective field. At small N/sub inv/, instead, mobility of SOI transistors exhibits a systematic reduction with decreasing T/sub SI/. The possible explanation for this /spl mu//sub eff/ degradation in extremely thin silicon layers is discussed by means of a comparison to previously published experimental data and theoretical calculations. Our analysis suggests a significant role is played by an enhancement of phonon scattering due to carrier confinement in the thinnest semiconductor films. The experimental mobility data have then been used to study the possible implications for ultrashort SOI transistor performance using numerical simulations.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

In this paper, we report an experimental investigation of electron mobility in ultrathin SOI MOSFETs operated in double-gate mode. Mobility is measured for silicon thickness down to approximately 5 nm and for different temperatures. Mobility data in single- and double-gate mode are then compared according to two different criteria imposing either the same total inversion charge density or the same effective field in the two operating modes. Our results demonstrate that for silicon films around 10 nm or thinner and at small inversion densities, a modest but unambiguous mobility improvement for double-gate mode operation is observed even if the same effective field as in the single-gate mode is kept. Furthermore, we also document that the mobility in double-gate mode can improve markedly above single-gate mobility when the comparison is made at the same total inversion density. This latter feature of the double-gate operating mode can be very beneficial in the perspective of very-low voltage operation.

Multisubband Monte Carlo Study of Transport, Quantization, and Electron-Gas Degeneration in Ultrathin SOI n-MOSFETs

This paper presents a new self-consistent multisubband Monte Carlo model for electronic transport in the inversion layer of decananometric MOSFETs. The simulator is 2D in real space and in k-space and accounts for the electron-gas degeneracy in the k-space. Simulation of nanoscale ultra-thin-body silicon-on-insulator MOSFETs shows that the subband structure and the carrier degeneracy strongly affect the transport properties and, in particular, the injection velocity and the channel back-scattering

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation

We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.

Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.

Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained.

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.