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Dive into the research topics where F. Danneville is active.

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Featured researches published by F. Danneville.


IEEE Electron Device Letters | 2003

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

G. Dambrine; C. Raynaud; Dimitri Lederer; Morin Dehan; O Rozeaux; M. Vanmackelberg; F. Danneville; Sylvie Lepilliet; Jean-Pierre Raskin

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.


IEEE Transactions on Microwave Theory and Techniques | 1993

A new method for on wafer noise measurement

Gilles Dambrine; Henri Happy; F. Danneville; A. Cappy

A method for measuring the noise parameters of MESFETs and HEMTs is presented. It is based on the fact that three independent noise parameters are sufficient to fully describe the device noise performance. It is shown that two noise parameters, R/sub n/ and mod Y/sub OPT/ mod , can be directly obtained from the frequency variation of the noise figure F/sub 50/ corresponding to a 50 Omega generator impedance. By using a theoretical relation between the intrinsic noise sources as additional data, the F/sub 50/ measurement only can provide the four noise parameters. A good agreement with more conventional techniques is obtained. >


IEEE Transactions on Electron Devices | 2006

Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs

Benjamin Iniguez; T.A. Fjeldly; A. Lazaro; F. Danneville; M.J. Deen

Compact-modeling principles and solutions for nanoscale double-gate and gate-all-around MOSFETs are explained. The main challenges of compact modeling for these devices are addressed, and different approaches for describing the electrostatics, the transport mechanisms, and the high-frequency behavior are explained. Several approximations used to derive analytical solutions of Poissons equation for doped and undoped devices are discussed, and the need for self-consistency with Schrodingers equation and with the current continuity equation resulting from the transport models is addressed. Several techniques to extend the compact modeling to the high-frequency regime and to study the RF performance, including noise, are presented and discussed


international electron devices meeting | 2007

Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs

Guilhem Larrieu; Emmanuel Dubois; Raphael Valentin; Nicolas Breil; F. Danneville; G. Dambrine; Jean-Pierre Raskin; J.C. Pesant

This paper proposes the implementation of a dopant segregated band-edge silicide using implantation-to-silicide and low temperature activation (500degC). The integration of platinum silicide coupled to boron segregation demonstrates a 50% enhancement of the current drive over the dopant-free approach. RF characterization unveils a cut-off frequency fT of 180 GHz at Lg=30 nm without application of channel stressors.


IEEE Transactions on Electron Devices | 2000

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Jung-Suk Goo; Chang-Hoon Choi; F. Danneville; E. Morifuji; H.S. Momose; Zhiping Yu; Hiroshi Iwai; Thomas H. Lee; Robert W. Dutton

Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.


IEEE Journal of Solid-state Circuits | 2005

230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications

Pascal Chevalier; Cyril Fellous; Laurent Rubaldo; Franck Pourchon; S. Pruvost; Rudy Beerkens; Fabienne Saguin; Nicolas Zerounian; B. Barbalat; Sylvie Lepilliet; Didier Dutartre; D. Celi; I. Telliez; Daniel Gloria; F. Aniel; F. Danneville; Alain Chantre

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.


IEEE Transactions on Electron Devices | 1999

High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits

Gilles Dambrine; Jean-Pierre Raskin; F. Danneville; D. Vanhoenackel Janvier; Jean-Pierre Colinge; A. Cappy

An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown.


Solid-state Electronics | 1995

Influence of the gate leakage current on the noise performance of MESFETs and MODFETs

F. Danneville; Gilles Dambrine; Henri Happy; Patrick Tadyszak; A. Cappy

Abstract In this paper, the influence of the gate leakage current on the noise performance of MESFETs and MODFETs is investigated. Both a simple analytical model and a more realistic numerical model have been developed. It is shown that the noise performance is strongly dependent on the gate leakage current value, especially at low frequency. The theoretical results are discussed and compared with experimental ones.


IEEE Transactions on Electron Devices | 2008

High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

Jean-Pierre Raskin; Guillaume Pailloncy; Dimitri Lederer; F. Danneville; Gilles Dambrine; Stefaan Decoutere; Abdelkarim Mercha; Bertrand Parvais

In this paper, the first-ever published investigation on radio-frequency (RF) noise performance of FinFETs is reported. The impact of the geometrical dimensions of FinFETs on RF noise parameters such as the channel length, the fin width, as well as the fin number is analyzed. A minimum noise figure of 1.35 dB is obtained with an associated available gain of 13.5 dB at 10 GHz for Vdd = 0.5 V. This result is quite encouraging to bring solutions for future low-power RF systems.


IEEE Transactions on Electron Devices | 2009

Analog/RF Performance of Multichannel SOI MOSFET

Tao Chuan Lim; Emilie Bernard; Olivier Rozeau; T. Ernst; B. Guillaumot; Nathalie Vulliet; Christel Buj-Dufournet; Michel Paccaud; Sylvie Lepilliet; Gilles Dambrine; F. Danneville

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

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G. Dambrine

Centre national de la recherche scientifique

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Jean-Pierre Raskin

Université catholique de Louvain

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A. Cappy

Centre national de la recherche scientifique

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Emmanuel Dubois

Centre national de la recherche scientifique

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Tao Chuan Lim

Centre national de la recherche scientifique

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