Tao Chuan Lim

Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

RF Small-Signal Analysis of Schottky-Barrier p-MOSFET

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer -parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a -gate-length SB MOSFET. Then, using ac simulations, HF FoMs sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key ac-element (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs.

First Internal Spacers' Introduction in Record High

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I_ON/I_OFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance <i>C</i> _gg reduction of 32% is measured, thanks to <i>S</i>-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain <i>A</i> _VI( = <i>gm</i>/<i>g</i> _ds) is improved by 92%.

I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}

In this letter, we propose a design methodology to enhance the High Frequency noise performance of the traditional CMOS technology via channel engineering. We show that the intrinsic noise correlation coefficient (C) of the conventional CMOS (~0.4 or lower) limits the noise performance. By lateral nonuniformly doping the channel, this value of C can be enhanced to as high as ~0.9 in the weak inversion regime and this in turn improves the NFmin of the device. Key noise parameters are carefully compared and analyzed in detail with the state-of-the-art GaAs-based pHEMT and nanoscaled CMOS technology. This letter offers another viable option for achieving CMOS with low power, low voltage, and with much improved noise performance without the need to scale the device.

Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS - also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (NF min) as compared to classical MOSFET transistors (with the same gate length Lg = 0.5 mum). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5- mum-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-mum-gate-length classical nMOS transistors.

MOSFETs RF Noise Optimization via Channel Engineering

Recent studies of Lim et al. have shown that channel engineering can effectively be used to globally improve the device noise performance. This happens because the doping profile can strongly impact the correlation between the drain and induced gate noise. In this brief, we will use the theory developed in the recent works of Roy et al. to provide a physical understanding and insight on the behavior of the gate-drain correlation coefficient, which will be very useful for understanding the mechanism by which the doping profile impacts the RF noise performance of a MOSFET.

Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs

For the first time, the high frequency (HF) performance of an ultra-thinned body (UTB) fully depleted silicon-on-insulator (FDSOI) incorporating TiN/HfO2 gate stack is reported. UTB-FDSOI with longer unit width Wu (same total width Wtot) features (results in) higher gm leading to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high-K dielectric and silicon, the measured transition frequency (fT) still correspond well to that predicted from the ITRS roadmap, and can also be considered as the first ever experimental fT measured fit for the Low STand-by Power (LSTP)-based RF/mobile application.

Impact of Lateral Asymmetry of MOSFETs on the Gate–Drain Noise Correlation

In this brief, it is clearly demonstrated that a two-parameter noise model is sufficient to accurately extract the MOSFET high-frequency noise performance, as long as channel uniformity is ensured (which corresponds to mainstream CMOS technology). Nevertheless, in the case of asymmetric channel-based MOSFETs, it is shown that a three-parameter noise model is required.

HF characterisation of sub-100nm UTB-FDSOI with TiN/HfO 2 gate stack

In this paper, the High Frequency (HF) Noise Performance of Silicon (Si) MOSFET are described in a first part through the DC biasing variations of key noise parameters related to physical noise sources or more circuit oriented such NFmin, the minimum noise figure. The second part highlights the fundamental difference between Si MOSFET and III‐V HEMT lies in the correlation coefficient C between intrinsic current noise sources. The third part proposes an interesting optimization of MOSFET HF noise performance through channel engineering before conclusion.

Thermal Noise in MOSFETs: A Two- or a Three-Parameter Noise Model?

Field effect transistors feature outstanding noise performance, and one of the fundamental reason being that the (input) gate noise is partially subtracted to the (output) drain noise. If III-V HEMTs strongly take benefit of this unique property, this is not the case for classical Si MOSFETs owing symmetric channel (SY-MOSFETs). In order to overcome this limitation, a new path to improve microwave noise performance of Si MOSFETs -through the use of laterally asymmetric channel- is proposed in this paper. The strong interest of these ldquoLAC-MOSFETsrdquo for low noise/low power applications is shown through a benchmarking of their noise properties/performances with SY-MOSFET and III-V pHEMTs.