F. Driussi

Analytical Models for the Insight Into the Use of Alternative Channel Materials in Ballistic nano-MOSFETs

This paper presents new analytical derivations for the ballistic current of n-MOSFETs as a function of the transport direction, of the properties of the channel material, and of the technological parameters. The main purpose of the analytical expressions is to provide an insight into the optimization of the transistors with alternative channel materials. Our results simply explain why, for a given two-dimensional (2-D) density of states, an elliptic 2-D minimum can provide a current larger than a circular minimum if the best transport direction is selected. Furthermore, we analytically show that the use of channel materials with very small transport masses implies a tradeoff between the electron velocity and the gate drive capacitance, because of the finite capacitance of the inversion layer. This latter effect should be seriously considered in the context of the aggressive scaling of the equivalent oxide thickness enforced by the introduction of high-K dielectrics and multigate MOSFETs

Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

We present a broad set of experiments on silicon nitride-based memories aimed at the investigation of the vertical position of the charge trapped in the nitride layer of silicon-oxide-nitride-oxide-semiconductor (SONOS) memories during program and erase in the tunneling regime. The results obtained for SONOS devices with conventional oxide-nitride-oxide and oxide-nitride-oxide-nitride-oxide gate stacks, as well as with high-top dielectric, have been validated by comparing different characterization techniques. It has been shown that, for SONOS cells, the charge centroid is located in the center of the silicon nitride layer, and its position is quite insensitive to the program or erase conditions and to the gate-stack composition.

Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells

A new characterization technique and an improved model for charge injection and transport through ONO gate stacks are used to investigate the program/retention sequence of silicon nitride-based (SONOS/TANOS) nonvolatile memories. The model accounts for drift-diffusion transport in the conduction band of silicon nitride (SiN). A priori assumptions on the spatial distribution of the charge at the beginning of the program/retention operations are not needed. We show that the carrier transport in the SiN layer impacts the spatial distribution of the trapped charge and, consequently, several aspects of program and retention transients. A few model improvements allow us to reconcile the apparent discrepancy between the values of silicon nitride trap energies extracted from program and retention experiments, thus reducing the number of model parameters.

Effects of Thermal Treatments on the Trapping Properties of HfO2 Films for Charge Trap Memories

The charge trapping properties of HfO2 thin films for application in charge trap memories are investigated as a function of high-temperature postdeposition annealing (PDA) and oxide thickness in the TaN/Al2O3/HfO2/SiO2/Si structure. The trap density (NT) in HfO2, extracted by simulating the programming transient, is in the 1019–1020 cm-3 range, and it is related to film thickness and PDA temperature. Diffusion phenomena in the stack play a significant role in modifying NT in HfO2 and the insulating properties of the Al2O3 layer. The memory performances for 1030 °C PDA are promising with respect to standard stacks featuring Si3N4.

A Quantitative Error Analysis of the Mobility Extraction According to the Matthiessen Rule in Advanced MOS Transistors

This paper presents a quantitative analysis of the errors produced by the Matthiessen rule in the extraction of the inversion-layer mobility in metal-oxide-semiconductor transistors. We show that the Matthiessen rule results in large inaccuracies in the mobility extraction, and most of all, it can lead to wrong trends, namely, to an incorrect dependence of the mobility on the temperature or the strain level. Consequently, when the Matthiessen rule is used to infer a given mobility component from the experiments, the inaccuracy of the extraction procedure can yield apparent discrepancies between experiments and simulations. Our results demonstrate that the mobility components extracted from the measurements by using the Matthiessen rule should not be regarded as experimental data because the extraction procedure relies on assumptions that are not fulfilled in most practical cases.

On the origin of the mobility reduction in n- and p-metal–oxide–semiconductor field effect transistors with hafnium-based/metal gate stacks

We examine the mobility reduction measured in hafnium-based dielectrics in n- and p-MOSFETs by means of extensive comparison between accurate multi-subband Monte Carlo simulations and experimental data for reasonably mature process technologies. We have considered scattering with remote (soft-optical) phonons and remote Coulomb interaction with single layers and dipole charges. A careful examination of model assumptions and limitations leads us to the conclusion that soft optical phonon scattering cannot quantitatively explain by itself the experimental mobility reduction reported by several groups for neither the electron nor the hole inversion layers. Experimental data can be reproduced only assuming consistently large concentrations of Coulomb scattering centers in the gate stack. However, the corresponding charge or dipole density would result in a large threshold voltage shift not observed in the experiments. We thus conclude that the main mechanisms responsible for the mobility reduction in MOSFETs ...

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO2 dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance

Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVMs—Part II: Atomistic and Electrical Modeling

Based on the material analysis of the SiN layers presented in part I of this paper, we develop accurate atomistic and electrical models for the silicon nitride (SiN)-based nonvolatile memory devices, taking into account the candidate SiN defects responsible for the memory effect. Our analysis points out the role of the hydrogen atoms and Si dangling bonds in the trapping properties of SiN films with different stoichiometries. The atomistic models provide a comprehensive picture describing the energy level and the occupation number of the different defects in the SiN. The electrical model coupled with the atomistic results, for the first time, demonstrates the ability to describe the program/erase curves of charge-trap memory cells with SiN storage layers with diversified composition. Good agreement between simulations and experimental results coming from the material analysis and the electrical characterization of thin (type-B device) and thick (type-A device) tunnel oxide memory cells is shown.

Damage generation and location in n- and p-MOSFETs biased in the Substrate-Enhanced Gate Current regime

This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel.

Simulation of DC and RF Performance of the Graphene Base Transistor

We examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain. To this purpose, we developed a model to calculate the current-voltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base-collector dielectrics that distort the potential profile and limit the upper value of fT. Model predictions are compared with available experiments. We show that, in spite of space charge high current effects, optimized GBT designs still hold the promise to achieve intrinsic cutoff frequency in the terahertz region, provided that an appropriate set of dielectric and emitter materials is chosen.